PCB Design Rules - kicad/aisler-hasl-2L.board-setup.json

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

Overview Files Skills Discover Packages Releases Dependencies Issues1 Breadcrumbs Pull Requests1 Activity

main

History Download

John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

{
  "vendor": "Aisler",
  "process": "hasl",
  "layerCount": 2,
  "boardSetupConstraints": {
    "minTrackWidthMm": 0.2,
    "minClearanceMm": 0.15,
    "minViaDrillMm": 0.3,
    "minViaDiameterMm": 0.7,
    "minHoleMm": 0.3,
    "copperEdgeClearanceMm": 0.3,
    "holeToHoleMm": 0.3,
    "annularRingViaMm": 0.2,
    "annularRingPadMm": null,
    "silkMinLineWidthMm": 0.15,
    "maskExpansionMm": 0.05
  },
  "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",
  "sources": [
    {
      "url": "https://community.aisler.net/t/2-layer-1-6-mm-35-m-hasl-design-rules/3735",
      "dateRead": "2026-09-03"
    }
  ]
}