PCB Design Rules - kicad/aisler-enig-2L.kicad_dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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(version 1)

# Aisler 2-layer design rules (enig process)
# 
# Min trace width: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish
# Min spacing: 0.125 mm (5.0 mil) - Cu 35um (1oz), ENIG finish
# Min drill: 0.25 mm (10.0 mil)
# Min via: 0.25 mm hole / 0.45 mm pad
# Annular ring: via 0.1 mm
# Copper to board edge: 0.3 mm
# Hole to hole: 0.3 mm
# Board thickness options: 1.6 mm
# Copper weight options: 1 oz
# Surface finishes: ENIG
# Max board size: 500 x 500 mm
# 
# Imperial measures are rounded from metric on the source page. Min board dimension greater than 10mm. Min SMD pad size 200um (8 mil). Copper to NPTH clearance 250um (10 mil), copper to NPTH slot clearance 300um (12 mil) for slots under and over 1.8mm. PTH drill range 0.5mm to 5.6mm, PTH annular ring 300um. Via drill range 0.25mm to 0.45mm, via annular ring 100um. NPTH drill range 0.5mm to 5.6mm. Min NPTH slot 0.8mm, min PTH slot 0.7mm, max PTH slot 2.6mm, PTH slot annular ring 300um. Min silkscreen text height 800um (32 mil). Max silkscreen coverage 25% per board side. Castellated edges supported free of charge. Green soldermask (Peters Elpemer AS 2467), buried, blind, micro, and tented vias not supported. Via pad diameter not published.
# 
# Sources:
# - https://community.aisler.net/t/2-layer-1-6mm-enig-design-rules/3732 (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.125mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.125mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.25mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.45mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.3mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.15mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))