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PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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pcb-design-rules / kicad / advanced-circuits-4pcb-advanced-standard-2L.kicad_dru
HistoryDownload
John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago
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(version 1)

# Advanced Circuits (4PCB) 2-layer design rules (advanced-standard process)
# 
# Min trace width: 0.1397 mm (5.5 mil) - outer layer, 1 oz Cu base; other weights: 0.0762 mm (3 mil) at 1/4 and 3/8 oz base, 0.1143 mm (4.5 mil) at 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)
# Min spacing: 0.1397 mm (5.5 mil) - outer layer trace to trace, 1 oz Cu base; 0.0762 mm (3 mil) at 1/4, 3/8, 1/2 oz base, 0.1778 mm (7 mil) at 2 oz, 0.2286 mm (9 mil) at 3 oz; inner layer 1 oz: 0.1143 mm (4.5 mil)
# Min drill: 0.1499 mm (5.9 mil)
# Min via: 0.1499 mm hole / 0.5309 mm pad
# Annular ring: via 0.1905 mm
# Copper to board edge: 0.254 mm
# Hole to hole: 0.3048 mm
# Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz
# Max board size: 406.4 x 558.8 mm
# 
# Capabilities table is per facility and per tier; this object is Santa Clara, CA, Standard column. Min board thickness 0.01 in (0.254 mm), max board thickness 0.25 in (6.35 mm). PTH tolerance plus or minus 0.003 in (0.0762 mm). Drill to copper for PTH 0.01 in (0.254 mm). Minimum pad 0.015 in (0.381 mm), minimum isolated pad 0.01 in (0.254 mm). Min copper sliver between antipads 0.005 in (0.127 mm). Aspect ratio plated through holes 10:1 for drilled greater than 0.020 in, 10:1 for 0.010 to 0.019 in. Other facilities differ, e.g. Maple Grove MN standard outer 1 oz trace width is 0.1016 mm (4 mil), smallest mech via 0.0043 in (0.1092 mm).
# 
# Sources:
# - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.1397mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.1397mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.1499mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.5309mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.254mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.1016mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))