PCB Design Rules - kicad/advanced-circuits-4pcb-advanced-2L.kicad_dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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(version 1)

# Advanced Circuits (4PCB) 2-layer design rules (advanced process)
# 
# Min trace width: 0.1016 mm (4.0 mil) - outer layer, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz base, 0.0762 mm (3 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz; inner 1 oz: 0.0889 mm (3.5 mil)
# Min spacing: 0.1016 mm (4.0 mil) - outer layer trace to trace, 1 oz Cu base; 0.0508 mm (2 mil) at 1/4 and 3/8 oz, 0.0635 mm (2.5 mil) at 1/2 oz, 0.1397 mm (5.5 mil) at 2 oz, 0.1905 mm (7.5 mil) at 3 oz
# Min drill: 0.127 mm (5.0 mil)
# Min via: 0.127 mm hole / 0.508 mm pad
# Annular ring: via 0.1905 mm
# Copper to board edge: 0.2032 mm
# Hole to hole: 0.254 mm
# Copper weight options: 0.25 oz, 0.375 oz, 0.5 oz, 1 oz, 2 oz, 3 oz, 4 oz
# Max board size: 482.6 x 558.8 mm
# 
# Santa Clara CA, Advanced tier. Max board size 19 x 22 in. Min board thickness 0.008 in (0.2032 mm). PTH tolerance plus or minus 0.002 in (0.0508 mm). Minimum pad 0.01 in (0.254 mm). Min outer layer trace for filled and plated over vias 0.004 in (0.1016 mm). Aspect ratio PTH 12:1.
# 
# Sources:
# - https://www.4pcb.com/pcb-capabilities.html (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.1016mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.1016mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.127mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.508mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.2032mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.0762mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))