skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
(version 1)
# Advanced Circuits (4PCB) 2-layer design rules (standard process)
#
# Min trace width: 0.127 mm (5.0 mil) - outer trace, standard spec
# Min spacing: 0.127 mm (5.0 mil) - standard spec trace/space 5/5 mils
# Min drill: 0.254 mm (10.0 mil)
# Min via: 0.254 mm hole
# Board thickness options: 0.7874 mm, 1.5748 mm, 2.3622 mm, 3.175 mm
# Copper weight options: 1 oz, 2 oz
# Surface finishes: Lead-Free HAL
# Max board size: 406.4 x 558.8 mm
#
# Standard spec: FR-4, 0 to 12 layers, IPC Class 2, quantity 1 to 10000 plus, turn time same day to 5 day. Hole tolerance plus or minus 0.005 in (0.127 mm). Rout tolerance plus or minus 0.010 in (0.254 mm). Solder mask LPI green, legend white. Board thickness options 0.031, 0.062, 0.093, 0.125 in. Standard finish pricing assumes lead-free HAL; ENIG or immersion silver at no extra cost if HAL unavailable. Same spec applies to 2 and 4 layer; page does not differentiate by layer count below 12.
#
# Sources:
# - https://www.4pcb.com/laminate-material-vendors.html (read 2026-09-03)
(rule "min-track-width"
(constraint track_width (min 0.127mm))
(layer "*.Cu")
(condition "A.type == 'track'"))
(rule "min-clearance"
(constraint clearance (min 0.127mm))
(condition "A.type == 'track' && B.type == 'track'"))
(rule "min-hole"
(constraint hole (min 0.254mm))
(condition "A.type == 'pad' || A.type == 'via'"))