PCB Design Rules - fusion/sierra-circuits-2L.dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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description[Sierra Circuits 2-layer design rules (standard process) |  | Min trace width: 0.1016 mm (4.0 mil) - STANDARD tier | Min spacing: 0.1016 mm (4.0 mil) - STANDARD tier | Min drill: 0.15 mm (5.9 mil) | Min via: 0.15 mm hole / 0.4547 mm pad | Annular ring: via 0.0254 mm | Copper to board edge: 0.254 mm | Board thickness options: 0.254 mm, 7.62 mm | Copper weight options: 4 oz | Surface finishes: HASL, Lead-Free HASL, OSP (Shikoku F2), OSP (Entek), ENIG, Immersion Silver, Electrolytic Soft Gold, Electrolytic Hard Gold, Selective Gold | Max board size: 304.8 x 457.2 mm |  | Values from the rigid PCB STANDARD tier table, published per process tier, not broken out by layer count, so 2-layer uses the same STANDARD values. Min board thickness 0.010 in (0.254 mm), max 0.300 in (7.62 mm). Max finished copper: outer layer 4 oz, inner layer 4 oz, min starting foil 3 microns. Min via pad derived from published process pad formula D plus 0.012 in, i.e. min drill 5.9 mil plus 12 mil. Annular ring 1 mil as stated in the process pad row. Max panel size STANDARD tier 12 x 18 in. Smallest laser drill 5 mil (0.127 mm), min finished hole 4 mil (0.102 mm). Solder mask registration 2 mil (0.0508 mm), solder mask feature tolerance 1.5 mil (0.0381 mm). |  | Sources: | - https://www.protoexpress.com/products/rigid-pcb/ (read 2026-09-03)]

layerSetup = (1*16)
mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm
mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
mdWireWire = 4.0mil
mdWirePad = 4.0mil
mdWireVia = 4.0mil
mdPadPad = 5.91mil
mdPadVia = 4.0mil
mdViaVia = 4.0mil
mdSmdPad = 4.0mil
mdSmdVia = 4.0mil
mdSmdSmd = 4.0mil
mdCopperDimension = 10.0mil
mdDrill = 7.87mil
msWidth = 4.0mil
msDrill = 5.91mil
mdViaViaSameLayer = 6mil
mdSmdStop = 0mil
msMicroVia = 12mil
msBlindViaRatio = 0.5
rvPadTop = 0
rvPadInner = 0
rvPadBottom = 0
rvViaOuter = 0
rvViaInner = 0
rvMicroViaOuter = 0
rvMicroViaInner = 0
rlMinPadTop = 7.09mil
rlMaxPadTop = 80mil
rlMinPadInner = 7.09mil
rlMaxPadInner = 20mil
rlMinPadBottom = 7.09mil
rlMaxPadBottom = 80mil
rlMinViaOuter = 1.0mil
rlMaxViaOuter = 20mil
rlMinViaInner = 1.0mil
rlMaxViaInner = 20mil
rlMinMicroViaOuter = 1.0mil
rlMaxMicroViaOuter = 20mil
rlMinMicroViaInner = 1.0mil
rlMaxMicroViaInner = 20mil
psTop = -1
psBottom = -1
psFirst = -1
psElongationLong = 100
psElongationOffset = 100
mvStopFrame = 0
mvCreamFrame = 0
mlMinStopFrame = 1.5mil
mlMaxStopFrame = 4mil
mlMinCreamFrame = 0mil
mlMaxCreamFrame = 0mil
mlViaStopLimit = 20mil
srRoundness = 0
srMinRoundness = 0mil
srMaxRoundness = 0mil
slThermalIsolate = 10mil
slThermalsForVias = 0
dpMaxLengthDifference = 400mil
dpGapFactor = 2.5
checkAngle = 0
checkRestrict = 1
checkStop = 0
checkValues = 0
checkNames = 1
checkWireStubs = 1
checkPolygonWidth = 0
useDiameter = 13
maxErrors = 50