skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
main
John Lauer
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
bafc3ce
1mo ago
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071
description[Seeed Fusion 2-layer design rules (standard process) | | Min trace width: 0.1016 mm (4.0 mil) - 1 oz copper, 4/4 mil option | Min spacing: 0.1016 mm (4.0 mil) - 1 oz copper, 4/4 mil option | Min drill: 0.2 mm (7.87 mil) | Min via: 0.2 mm hole / 0.4 mm pad | Annular ring: via 0.1 mm | Copper to board edge: 0.3 mm | Hole to hole: 0.3 mm | Board thickness options: 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm, 2.5 mm, 3.0 mm | Copper weight options: 1 oz, 2 oz, 3 oz | Surface finishes: HASL, HASL lead-free, ENIG, OSP, Hard Gold | Max board size: 500 x 500 mm | | Trace width/spacing by copper weight: 1 oz: 4/4, 5/5, or 6/6 mil options (0.1016/0.127/0.1524 mm); 2 oz: 10/10 mil (0.254 mm); 3 oz: 15/15 mil (0.381 mm). RF coil designs require 6/6 mil but select 4/4 mil option. Min board size 10 x 10 mm. Drill ranges: NPTH 0.2 to 6.3 mm, PTH 0.2 to 5.8 mm, via holes 0.2 to 0.5 mm (vias 0.3 mm and smaller guarantee full mask tenting). Min via pad not published directly, min annular ring 0.1 mm implies pad = drill + 0.2 mm. Min plated slot 0.65 mm, non-plated slot 0.8 mm. BGA pitch guidance: 0.45 mm pitch with 6/6 mil, 0.35 mm with 5/5 mil, 0.25 mm with 4/4 mil. | | Sources: | - https://support.seeed.cc/portal/en/kb/articles/fusion-pcb-specification (read 2026-09-03) | - https://www.seeedstudio.com/fusion_pcb.html (read 2026-09-03)]
layerSetup = (1*16)
mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm
mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
mdWireWire = 4.0mil
mdWirePad = 4.0mil
mdWireVia = 4.0mil
mdPadPad = 5.91mil
mdPadVia = 4.0mil
mdViaVia = 4.0mil
mdSmdPad = 4.0mil
mdSmdVia = 4.0mil
mdSmdSmd = 4.0mil
mdCopperDimension = 11.81mil
mdDrill = 11.81mil
msWidth = 4.0mil
msDrill = 7.87mil
mdViaViaSameLayer = 6mil
mdSmdStop = 0mil
msMicroVia = 12mil
msBlindViaRatio = 0.5
rvPadTop = 0
rvPadInner = 0
rvPadBottom = 0
rvViaOuter = 0
rvViaInner = 0
rvMicroViaOuter = 0
rvMicroViaInner = 0
rlMinPadTop = 7.09mil
rlMaxPadTop = 80mil
rlMinPadInner = 7.09mil
rlMaxPadInner = 20mil
rlMinPadBottom = 7.09mil
rlMaxPadBottom = 80mil
rlMinViaOuter = 3.94mil
rlMaxViaOuter = 20mil
rlMinViaInner = 3.94mil
rlMaxViaInner = 20mil
rlMinMicroViaOuter = 3.94mil
rlMaxMicroViaOuter = 20mil
rlMinMicroViaInner = 3.94mil
rlMaxMicroViaInner = 20mil
psTop = -1
psBottom = -1
psFirst = -1
psElongationLong = 100
psElongationOffset = 100
mvStopFrame = 0
mvCreamFrame = 0
mlMinStopFrame = 1.5mil
mlMaxStopFrame = 4mil
mlMinCreamFrame = 0mil
mlMaxCreamFrame = 0mil
mlViaStopLimit = 20mil
srRoundness = 0
srMinRoundness = 0mil
srMaxRoundness = 0mil
slThermalIsolate = 10mil
slThermalsForVias = 0
dpMaxLengthDifference = 400mil
dpGapFactor = 2.5
checkAngle = 0
checkRestrict = 1
checkStop = 0
checkValues = 0
checkNames = 1
checkWireStubs = 1
checkPolygonWidth = 0
useDiameter = 13
maxErrors = 50