PCB Design Rules - fusion/jlcpcb-4L.dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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description[JLCPCB 4-layer design rules (standard process) |  | Min trace width: 0.09 mm (3.5 mil) - 1 oz copper outer layer, 3 mil acceptable in BGA fan-outs | Min spacing: 0.09 mm (3.5 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.15 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm | Copper weight options: 1 oz, 2 oz | Surface finishes: HASL leaded, HASL lead-free, ENIG | Max board size: 663 x 593 mm |  | Same source page as 2 layer, multilayer column. Inner layer copper 0.5/1/2 oz, 0.5 oz default. Inner layer via hole to copper clearance 0.2 mm, inner PTH pad hole to copper clearance 0.3 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Min plated slot width 0.35 mm multilayer. Controlled impedance available. Blind/buried vias not supported, through holes only. |  | Sources: | - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)]

layerSetup = (1*2*15*16)
mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm
mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
mdWireWire = 3.54mil
mdWirePad = 3.54mil
mdWireVia = 3.54mil
mdPadPad = 5.91mil
mdPadVia = 3.54mil
mdViaVia = 3.54mil
mdSmdPad = 3.54mil
mdSmdVia = 3.54mil
mdSmdSmd = 3.54mil
mdCopperDimension = 7.87mil
mdDrill = 7.87mil
msWidth = 3.54mil
msDrill = 5.91mil
mdViaViaSameLayer = 6mil
mdSmdStop = 0mil
msMicroVia = 12mil
msBlindViaRatio = 0.5
rvPadTop = 0
rvPadInner = 0
rvPadBottom = 0
rvViaOuter = 0
rvViaInner = 0
rvMicroViaOuter = 0
rvMicroViaInner = 0
rlMinPadTop = 7.09mil
rlMaxPadTop = 80mil
rlMinPadInner = 7.09mil
rlMaxPadInner = 20mil
rlMinPadBottom = 7.09mil
rlMaxPadBottom = 80mil
rlMinViaOuter = 5.91mil
rlMaxViaOuter = 20mil
rlMinViaInner = 5.91mil
rlMaxViaInner = 20mil
rlMinMicroViaOuter = 5.91mil
rlMaxMicroViaOuter = 20mil
rlMinMicroViaInner = 5.91mil
rlMaxMicroViaInner = 20mil
psTop = -1
psBottom = -1
psFirst = -1
psElongationLong = 100
psElongationOffset = 100
mvStopFrame = 0
mvCreamFrame = 0
mlMinStopFrame = 1.5mil
mlMaxStopFrame = 4mil
mlMinCreamFrame = 0mil
mlMaxCreamFrame = 0mil
mlViaStopLimit = 20mil
srRoundness = 0
srMinRoundness = 0mil
srMaxRoundness = 0mil
slThermalIsolate = 10mil
slThermalsForVias = 0
dpMaxLengthDifference = 400mil
dpGapFactor = 2.5
checkAngle = 0
checkRestrict = 1
checkStop = 0
checkValues = 0
checkNames = 1
checkWireStubs = 1
checkPolygonWidth = 0
useDiameter = 13
maxErrors = 50