PCB Design Rules - fusion/jlcpcb-2L.dru

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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description[JLCPCB 2-layer design rules (standard process) |  | Min trace width: 0.1 mm (4.0 mil) - 1 oz copper outer layer | Min spacing: 0.1 mm (4.0 mil) - 1 oz copper, different nets | Min drill: 0.15 mm (5.91 mil) | Min via: 0.15 mm hole / 0.25 mm pad | Annular ring: via 0.18 mm | Copper to board edge: 0.2 mm | Hole to hole: 0.2 mm | Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm | Copper weight options: 1 oz, 2 oz, 2.5 oz, 3.5 oz, 4.5 oz | Surface finishes: HASL leaded, HASL lead-free, ENIG | Max board size: 670 x 600 mm |  | 2 oz: min trace/spacing 0.16/0.16 mm (6.5/6.5 mil). 2.5 oz: 0.2/0.2 mm (8/8 mil). 3.5 oz: 0.25/0.25 mm (10/10 mil). 4.5 oz: 0.3/0.3 mm (12/12 mil). Min drill 0.15 mm costs more. Via diameter should be 0.1 mm (0.15 mm preferred) larger than via hole, preferred min via hole 0.2 mm. PTH annular ring 2 oz: 0.254 mm or above. NPTH pad annular ring 0.45 mm recommended. Min NPTH 0.5 mm. Min plated slot width 0.5 mm. Pad to track clearance 0.1 mm. SMD pad to pad clearance different nets 0.15 mm. Via hole to track 0.2 mm, PTH to track 0.28 mm (0.35 recommended), NPTH to track 0.2 mm. Same-net track spacing 0.25 mm. Min silk text height 1.0 mm (40 mil). Soldermask opening to neighboring trace clearance 0.09 mm. Trace width tolerance plus/minus 20 percent. |  | Sources: | - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)]

layerSetup = (1*16)
mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm
mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
mdWireWire = 3.94mil
mdWirePad = 3.94mil
mdWireVia = 3.94mil
mdPadPad = 5.91mil
mdPadVia = 3.94mil
mdViaVia = 3.94mil
mdSmdPad = 3.94mil
mdSmdVia = 3.94mil
mdSmdSmd = 3.94mil
mdCopperDimension = 7.87mil
mdDrill = 7.87mil
msWidth = 3.94mil
msDrill = 5.91mil
mdViaViaSameLayer = 6mil
mdSmdStop = 0mil
msMicroVia = 12mil
msBlindViaRatio = 0.5
rvPadTop = 0
rvPadInner = 0
rvPadBottom = 0
rvViaOuter = 0
rvViaInner = 0
rvMicroViaOuter = 0
rvMicroViaInner = 0
rlMinPadTop = 7.09mil
rlMaxPadTop = 80mil
rlMinPadInner = 7.09mil
rlMaxPadInner = 20mil
rlMinPadBottom = 7.09mil
rlMaxPadBottom = 80mil
rlMinViaOuter = 7.09mil
rlMaxViaOuter = 20mil
rlMinViaInner = 7.09mil
rlMaxViaInner = 20mil
rlMinMicroViaOuter = 7.09mil
rlMaxMicroViaOuter = 20mil
rlMinMicroViaInner = 7.09mil
rlMaxMicroViaInner = 20mil
psTop = -1
psBottom = -1
psFirst = -1
psElongationLong = 100
psElongationOffset = 100
mvStopFrame = 0
mvCreamFrame = 0
mlMinStopFrame = 1.5mil
mlMaxStopFrame = 4mil
mlMinCreamFrame = 0mil
mlMaxCreamFrame = 0mil
mlViaStopLimit = 20mil
srRoundness = 0
srMinRoundness = 0mil
srMaxRoundness = 0mil
slThermalIsolate = 10mil
slThermalsForVias = 0
dpMaxLengthDifference = 400mil
dpGapFactor = 2.5
checkAngle = 0
checkRestrict = 1
checkStop = 0
checkValues = 0
checkNames = 1
checkWireStubs = 1
checkPolygonWidth = 0
useDiameter = 13
maxErrors = 50