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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago
description[Eurocircuits 2-layer design rules (proto process) |  | Min trace width: 0.15 mm (5.91 mil) - all services, pattern class 6 | Min spacing: 0.15 mm (5.91 mil) - track to track, pattern class 6; class 5 is 0.175 mm (6.8898 mil), class 7 is 0.125 mm (4.9213 mil) | Min drill: 0.25 mm (9.84 mil) | Min via: 0.25 mm hole / 0.6 mm pad | Annular ring: via 0.125 mm | Copper to board edge: 0.25 mm | Hole to hole: 0.25 mm | Board thickness options: 1.55 mm | Copper weight options: 0.5 oz, 1 oz | Surface finishes: ENIG, LF HAL | Max board size: 580 x 425 mm |  | Min board 20 x 20 mm. Base copper foil: outer layers 18 µm (0.5 oz), inner layers 35 µm (1 oz). Minimum pad diameter: PTH is finished hole plus 0.350 mm on outer and inner layers, NPTH is finished hole plus 0.250 mm. Tool size equals finished PTH hole size plus 0.10 mm (4 mil), NPTH tool size equals finished size. Drill bits in 0.05 mm increments. Standard PTH hole tolerance plus/minus 0.10 mm (0.20 mm range) for holes 4 mm or less, NPTH plus/minus 0.05 mm. Holes with finished size 0.45 mm or smaller are defined as via holes. Pattern class 5 (all services): track/gap 0.175 mm (6.8898 mil), OAR/IAR 0.150 mm (5.9055 mil), IPI 0.225 mm (8.8583 mil). Legend to board edge: 0.250 mm routing, 0.450 mm scoring. Soldermask design rules LDI: pad to pad 0.135 mm (5.315 mil), track to pad 0.090 mm (3.5433 mil); PI colors: pad to pad 0.330 mm (12.9921 mil), track to pad 0.190 mm (7.4803 mil). Mask overlap clearance MOC: LDI 0.060 mm (2.3622 mil), PI 0.090 mm (3.5433 mil). |  | Sources: | - https://www.eurocircuits.com/services/pcb-proto/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/classification/ (read 2026-09-03) | - https://www.eurocircuits.com/content/uploads/2025/04/EC-classification-ENGLISH-5-2024-V3.png (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/drilled-holes/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/soldermask/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/legend-print/ (read 2026-09-03) | - https://www.eurocircuits.com/technical-guidelines/pcb-design-guidelines/copper-layers/ (read 2026-09-03)]

layerSetup = (1*16)
mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm
mtIsolate = 1.6mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
mdWireWire = 5.91mil
mdWirePad = 5.91mil
mdWireVia = 5.91mil
mdPadPad = 5.91mil
mdPadVia = 5.91mil
mdViaVia = 5.91mil
mdSmdPad = 5.91mil
mdSmdVia = 5.91mil
mdSmdSmd = 5.91mil
mdCopperDimension = 9.84mil
mdDrill = 9.84mil
msWidth = 5.91mil
msDrill = 9.84mil
mdViaViaSameLayer = 6mil
mdSmdStop = 0mil
msMicroVia = 12mil
msBlindViaRatio = 0.5
rvPadTop = 0
rvPadInner = 0
rvPadBottom = 0
rvViaOuter = 0
rvViaInner = 0
rvMicroViaOuter = 0
rvMicroViaInner = 0
rlMinPadTop = 7.09mil
rlMaxPadTop = 80mil
rlMinPadInner = 7.09mil
rlMaxPadInner = 20mil
rlMinPadBottom = 7.09mil
rlMaxPadBottom = 80mil
rlMinViaOuter = 4.92mil
rlMaxViaOuter = 20mil
rlMinViaInner = 4.92mil
rlMaxViaInner = 20mil
rlMinMicroViaOuter = 4.92mil
rlMaxMicroViaOuter = 20mil
rlMinMicroViaInner = 4.92mil
rlMaxMicroViaInner = 20mil
psTop = -1
psBottom = -1
psFirst = -1
psElongationLong = 100
psElongationOffset = 100
mvStopFrame = 0
mvCreamFrame = 0
mlMinStopFrame = 1.5mil
mlMaxStopFrame = 4mil
mlMinCreamFrame = 0mil
mlMaxCreamFrame = 0mil
mlViaStopLimit = 20mil
srRoundness = 0
srMinRoundness = 0mil
srMaxRoundness = 0mil
slThermalIsolate = 10mil
slThermalsForVias = 0
dpMaxLengthDifference = 400mil
dpGapFactor = 2.5
checkAngle = 0
checkRestrict = 1
checkStop = 0
checkValues = 0
checkNames = 1
checkWireStubs = 1
checkPolygonWidth = 0
useDiameter = 13
maxErrors = 50