PCB Design Rules - altium/osh-park-6L.RUL

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read… bafc3ce 1mo ago

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[Design Rules]
RuleCount=6

[Rule1]
RuleKind=Width
RuleName=MinTraceWidth
Scope1=All
Scope2=
Attribute=MinWidth=0.127mm|PreferredWidth=0.254mm|MaxWidth=25.4mm

[Rule2]
RuleKind=Clearance
RuleName=MinClearance
Scope1=All
Scope2=
Attribute=Clearance=0.127mm

[Rule3]
RuleKind=RoutingViaStyle
RuleName=MinVia
Scope1=All
Scope2=
Attribute=PreferredViaWidth=0.4064mm|PreferredViaHoleWidth=0.2032mm|MinViaWidth=0.4064mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.2032mm|MaxViaHoleWidth=6.35mm

[Rule4]
RuleKind=HoleSize
RuleName=MinHole
Scope1=All
Scope2=
Attribute=HoleWidth=0.2032mm

[Rule5]
RuleKind=AnnularRing
RuleName=MinAnnularRing
Scope1=All
Scope2=
Attribute=MinAnnularRing=0.1016mm

[Rule6]
RuleKind=BoardOutlineClearance
RuleName=CopperToBoardEdge
Scope1=All
Scope2=
Attribute=Clearance=0.381mm