skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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Delete kicad/adom-instapcb-2L.board-setup.json
1 file changed
−26
kicad/adom-instapcb-2L.board-setup.jsondeleted−26@@ -1,26 +0,0 @@-{- "vendor": "3rd party fab",- "process": "standard",- "layerCount": 2,- "boardSetupConstraints": {- "minTrackWidthMm": 0.1,- "minClearanceMm": 0.1,- "minViaDrillMm": 0.15,- "minViaDiameterMm": 0.25,- "minHoleMm": 0.15,- "copperEdgeClearanceMm": 0.2,- "holeToHoleMm": 0.2,- "annularRingViaMm": 0.1,- "annularRingPadMm": 0.18,- "silkMinLineWidthMm": null,- "maskExpansionMm": 0.038- },- "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",- "sources": [- {- "url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru",- "dateRead": "2026-09-03",- "kind": "bundled-rule-file"- }- ]-}