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PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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rules/records/adom-instapcb.jsondeleted−57@@ -1,57 +0,0 @@-{- "vendor": "3rd party fab",- "vendorSlug": "adom-instapcb",- "vendorUrl": null,- "records": [- {- "process": "standard",- "layerCount": 2,- "minTraceWidth": {"mm": 0.10, "mil": 3.94, "condition": "1 oz copper"},- "minSpacing": {"mm": 0.10, "mil": 3.94, "condition": "1 oz copper, different nets"},- "minDrill": {"mm": 0.15, "mil": 5.91},- "minVia": {"drillMm": 0.15, "drillMil": 5.91, "padMm": 0.25, "padMil": 9.84},- "annularRing": {"viaMm": 0.10, "viaMil": 3.94, "padMm": 0.18, "padMil": 7.09, "note": "0.25 mm or above preferred"},- "copperToBoardEdge": {"mm": 0.20, "mil": 7.87},- "holeToHole": {"mm": 0.20, "mil": 7.87},- "maskExpansion": {"mm": 0.038, "mil": 1.50},- "maskSliver": null,- "silkLineWidth": null,- "silkToCopper": null,- "minCopperClearance": {"mm": 0.10, "mil": 3.94, "condition": "different nets"},- "boardThicknessOptionsMm": [1.6],- "copperWeightOptionsOz": [1],- "surfaceFinishes": [],- "maxBoardSize": null,- "drillRange": {"minMm": 0.15, "maxMm": 6.3, "note": "holes with diameter >= 6.3 mm are CNC routed from a smaller drilled hole; min non-plated hole 0.50 mm"},- "notes": "Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.",- "sources": [- {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-rule-file"}- ]- },- {- "process": "standard",- "layerCount": 4,- "minTraceWidth": {"mm": 0.09, "mil": 3.54, "condition": "1 oz copper, multilayer"},- "minSpacing": {"mm": 0.09, "mil": 3.54, "condition": "1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs"},- "minDrill": {"mm": 0.15, "mil": 5.91},- "minVia": {"drillMm": 0.15, "drillMil": 5.91, "padMm": 0.25, "padMil": 9.84},- "annularRing": {"viaMm": 0.10, "viaMil": 3.94, "padMm": 0.18, "padMil": 7.09, "note": "0.25 mm or above preferred"},- "copperToBoardEdge": {"mm": 0.20, "mil": 7.87},- "holeToHole": {"mm": 0.20, "mil": 7.87},- "maskExpansion": {"mm": 0.038, "mil": 1.50},- "maskSliver": null,- "silkLineWidth": null,- "silkToCopper": null,- "minCopperClearance": {"mm": 0.09, "mil": 3.54, "condition": "different nets"},- "boardThicknessOptionsMm": [1.6],- "copperWeightOptionsOz": [1],- "surfaceFinishes": [],- "maxBoardSize": null,- "drillRange": {"minMm": 0.15, "maxMm": 6.3, "note": "holes with diameter >= 6.3 mm are CNC routed from a smaller drilled hole; min non-plated hole 0.50 mm"},- "notes": "BGA pad diameter >= 0.25 mm. BGA pad to trace clearance min 0.09 mm. Vias can be placed within BGA pads using filled and plated-over vias.",- "sources": [- {"url": "adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-4-Layer.edru", "dateRead": "2026-09-03", "kind": "bundled-rule-file"}- ]- }- ]-}