skill
PCB Design Rules
Public Made by Adomby adom
Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.
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kicad/adom-instapcb-2L.kicad_drudeleted−40@@ -1,40 +0,0 @@-(version 1)--# 3rd party fab 2-layer design rules (standard process)-# -# Min trace width: 0.1 mm (3.94 mil) - 1 oz copper-# Min spacing: 0.1 mm (3.94 mil) - 1 oz copper, different nets-# Min drill: 0.15 mm (5.91 mil)-# Min via: 0.15 mm hole / 0.25 mm pad-# Annular ring: via 0.1 mm, pad 0.18 mm-# Copper to board edge: 0.2 mm-# Hole to hole: 0.2 mm-# Drill range: 0.15 mm to 6.3 mm-# Board thickness options: 1.6 mm-# Copper weight options: 1 oz-# -# Baseline of the 3rd party fab service. Preferred values in the seed file: default class preferred track 0.2 mm, power class preferred 0.3 mm; preferred via hole 0.2 mm (0.25 mm in the shipped file). Min via allowed on 2-layer.-# -# Sources:-# - adom/fusion-bridge addin/AdomBridge/resources/dru/Adom-InstaPCB-2-Layer.edru (read 2026-09-03)--(rule "min-track-width"- (constraint track_width (min 0.1mm))- (layer "*.Cu")- (condition "A.type == 'track'"))--(rule "min-clearance"- (constraint clearance (min 0.1mm))- (condition "A.type == 'track' && B.type == 'track'"))--(rule "min-hole"- (constraint hole (min 0.15mm))- (condition "A.type == 'pad' || A.type == 'via'"))--(rule "min-via-diameter"- (constraint via_diameter (min 0.25mm))- (condition "A.type == 'via'"))--(rule "min-edge-clearance"- (constraint edge_clearance (min 0.2mm))- (condition "A.type == 'track'"))