EDA Skillpack
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All skills for all EDA capabilities across the Adom ecosystem.
Astra ESC current and thermal screening source
Read the qualification review.
Result: not qualified. The 58.5 A screening case exposes excessive +VBAT feed resistance. This is a board-specific analysis example, not a validated universal solver, a physical test, or a manufacturing release. The original board/video is preserved.
Reproduce locally
Clone the existing adom/eda-engineering page and work in docs/examples/astra-esc-independent. The parent directory supplies geometry.py, fixture_geometry.py, route-input.kicad_pcb and the recorded final state under evidence/. No remote desktop is required to rerun the models from the provided refilled board.
python3 -m pip install --target thermal/vendor -r thermal/requirements.txt
python3 thermal/extract_copper.py
python3 thermal/benchmark_dc.py
python3 thermal/dc_model.py .15 .025
python3 thermal/dc_model.py .10 .025
DC_NET=+VBAT python3 thermal/dc_model.py .075 .025
DC_NET=+VBAT python3 thermal/dc_model.py .075 .015
DC_NET=+VBAT python3 thermal/dc_model.py .075 .035
python3 thermal/thermal_screen.py .5
python3 thermal/thermal_screen.py .25
python3 thermal/plot_paths.py
python3 thermal/make_report.py
Use a suitable Python environment. vendor/ is an isolated optional dependency location, not distributed here. The extraction script creates a local trusted pickle of Shapely geometry. Never load an untrusted pickle. Heat maps are generated NumPy data, not native KiCad screenshots. Numerical solvers may vary slightly with platform/library versions.
dc_model.py reads terminals specific to this board and uses four coupled sheet resistor networks with plated barrels. It runs the thirteen listed paths, or one net selected by DC_NET. Outputs include conservation checks and per-unit-current heat maps. Grid size and plating are explicit CLI inputs. Before adapting to another board, replace source/sink definitions, bounding box, layer stack and material assumptions, verify geometry/contacts and repeat numerical validation.
thermal_screen.py is a prescribed-loss four-sheet screen. It uses the full 0.10 mm electrical results and balanced six-step averaging. It approximates dielectric conduction, copper fractions and film cooling. See REPORT.md for omitted physical effects, uncertain inputs and mesh sensitivity. The output is not a junction-temperature certification.
Native reconstruction and validation used for this review
rebuild_native.py runs with KiCad's Python, next to the supplied geometry-input.json and the analysis route-input.kicad_pcb. It writes only astra-analysis-refilled.kicad_pcb. It does not open or save the original live fixture. On the named test desktop the Python executable was:
C:/Users/arav/AppData/Local/Programs/KiCad/10.0/bin/python.exe
The analysis directory was:
C:/Users/arav/Downloads/adom-gate/esc-demo/astra-thermal-analysis
The successful native script output is preserved in native-rebuild2-result.json. The dedicated read-only DRC command was:
adom-bridge --ai-thread "Astra ESC thermal qualification" --target arav-rog kicad_run_drc '{"filePath":"C:/Users/arav/Downloads/adom-gate/esc-demo/astra-thermal-analysis/astra-analysis-refilled.kicad_pcb","refillZones":false}'
analysis-native-drc.json preserves the result. filled-area-parity.json compares native reconstructed fills to the recorded fills. The final file hash and counted items are in the report/summary.
Attempts and limitations retained
The first reconstruction attempted a nonexistent pcbnew setter, SetDoNotAllowCopperPour. It failed before saving the board. Inspection of the native API led to the correct SetDoNotAllowZoneFills call; the successful reconstruction retains all keepouts. Generic shell DRC subsequently lost authorization during a Bridge restart; the dedicated read-only KiCad DRC verb succeeded. A transient offline pull was retried after rediscovering arav-rog. No other desktop or original board was substituted.
The first plotting pass hid the computed image beneath copper patches. Plot z-order was corrected and the rendered image inspected. Earlier map files omitted plating from the filename; final code includes it. The first 0.50 mm thermal output used thermal-screen.json; the identical result was copied to the final thermal-screen-0.5.json convention. These are analysis/plotting corrections, not changes to the recorded board or Bridge software.
Full model source and results are ordinary files in the existing EDA Skillpack repository, available to any AI. No new package or private Bridge patch was created. Existing thermal/current-review skills already require these checks. This follow-up does not alter the placement/routing benchmark timings or costs. No AI subagents were spawned.
# Astra ESC current and thermal screening source
[Read the qualification review](https://wiki.adom.inc/adom/codex/files/docs/ASTRA-ESC-THERMAL.md).
Result: not qualified. The 58.5 A screening case exposes excessive +VBAT feed resistance. This is a board-specific analysis example, not a validated universal solver, a physical test, or a manufacturing release. The original board/video is preserved.
## Reproduce locally
Clone the existing `adom/eda-engineering` page and work in `docs/examples/astra-esc-independent`. The parent directory supplies `geometry.py`, `fixture_geometry.py`, `route-input.kicad_pcb` and the recorded final state under `evidence/`. No remote desktop is required to rerun the models from the provided refilled board.
```bash
python3 -m pip install --target thermal/vendor -r thermal/requirements.txt
python3 thermal/extract_copper.py
python3 thermal/benchmark_dc.py
python3 thermal/dc_model.py .15 .025
python3 thermal/dc_model.py .10 .025
DC_NET=+VBAT python3 thermal/dc_model.py .075 .025
DC_NET=+VBAT python3 thermal/dc_model.py .075 .015
DC_NET=+VBAT python3 thermal/dc_model.py .075 .035
python3 thermal/thermal_screen.py .5
python3 thermal/thermal_screen.py .25
python3 thermal/plot_paths.py
python3 thermal/make_report.py
```
Use a suitable Python environment. `vendor/` is an isolated optional dependency location, not distributed here. The extraction script creates a local trusted pickle of Shapely geometry. Never load an untrusted pickle. Heat maps are generated NumPy data, not native KiCad screenshots. Numerical solvers may vary slightly with platform/library versions.
`dc_model.py` reads terminals specific to this board and uses four coupled sheet resistor networks with plated barrels. It runs the thirteen listed paths, or one net selected by `DC_NET`. Outputs include conservation checks and per-unit-current heat maps. Grid size and plating are explicit CLI inputs. Before adapting to another board, replace source/sink definitions, bounding box, layer stack and material assumptions, verify geometry/contacts and repeat numerical validation.
`thermal_screen.py` is a prescribed-loss four-sheet screen. It uses the full 0.10 mm electrical results and balanced six-step averaging. It approximates dielectric conduction, copper fractions and film cooling. See REPORT.md for omitted physical effects, uncertain inputs and mesh sensitivity. The output is not a junction-temperature certification.
## Native reconstruction and validation used for this review
`rebuild_native.py` runs with KiCad's Python, next to the supplied `geometry-input.json` and the analysis `route-input.kicad_pcb`. It writes only `astra-analysis-refilled.kicad_pcb`. It does not open or save the original live fixture. On the named test desktop the Python executable was:
```
C:/Users/arav/AppData/Local/Programs/KiCad/10.0/bin/python.exe
```
The analysis directory was:
```
C:/Users/arav/Downloads/adom-gate/esc-demo/astra-thermal-analysis
```
The successful native script output is preserved in `native-rebuild2-result.json`. The dedicated read-only DRC command was:
```bash
adom-bridge --ai-thread "Astra ESC thermal qualification" --target arav-rog kicad_run_drc '{"filePath":"C:/Users/arav/Downloads/adom-gate/esc-demo/astra-thermal-analysis/astra-analysis-refilled.kicad_pcb","refillZones":false}'
```
`analysis-native-drc.json` preserves the result. `filled-area-parity.json` compares native reconstructed fills to the recorded fills. The final file hash and counted items are in the report/summary.
## Attempts and limitations retained
The first reconstruction attempted a nonexistent pcbnew setter, `SetDoNotAllowCopperPour`. It failed before saving the board. Inspection of the native API led to the correct `SetDoNotAllowZoneFills` call; the successful reconstruction retains all keepouts. Generic shell DRC subsequently lost authorization during a Bridge restart; the dedicated read-only KiCad DRC verb succeeded. A transient offline pull was retried after rediscovering arav-rog. No other desktop or original board was substituted.
The first plotting pass hid the computed image beneath copper patches. Plot z-order was corrected and the rendered image inspected. Earlier map files omitted plating from the filename; final code includes it. The first 0.50 mm thermal output used `thermal-screen.json`; the identical result was copied to the final `thermal-screen-0.5.json` convention. These are analysis/plotting corrections, not changes to the recorded board or Bridge software.
Full model source and results are ordinary files in the existing EDA Skillpack repository, available to any AI. No new package or private Bridge patch was created. Existing thermal/current-review skills already require these checks. This follow-up does not alter the placement/routing benchmark timings or costs. No AI subagents were spawned.