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Astra ESC G431 current and thermal qualification review
Disposition: NOT QUALIFIED. The 58.5 A high-current screening case fails. No continuous or peak hardware current rating has been established. This follow-up evaluates Astra's independent placement, routing and pours from issue 96. It does not substitute Fable's placement or change the original layout/video benchmark.
The dominant finding is a poor +VBAT distribution path to Q1 and Q3. Large filled regions are connected through constricted copper and interlayer paths. A 0.075 mm electrical mesh gives 12.86 mΩ to Q1, 6.79 mΩ to Q3, and 0.506 mΩ to Q5 from input MC1.1. The Q1 path dissipates about 44.0 W while carrying 58.5 A at the assumed cold copper resistivity. That is an instantaneous conducting-state stress calculation, not its balanced-cycle average and not a claim about actual motor current.
Evidence and board identity
A separate native KiCad analysis copy was reconstructed from the recorded final segments, vias, placement and zone/keepout settings, then refilled on arav-rog. The original fixture was not saved or modified. Analysis copy SHA-256: 2ba0f80c7798d2ef37f5db37b2d849859149531efcc86125ae69e5a9b7b6ea32. KiCad 10.0.3, kicad-bridge 1.0.7. Native result: 2079 segments, 246 vias, 21 zone objects; 0 unconnected, 13 errors and 63 warnings. The 13 errors are the previously documented six Q1-Q6 malformed courtyards and seven U2 pad clearances. They remain unresolved manufacturing issues, not waived errors.
Native zone-filled areas reproduce the recorded result within 0.005 mm² per layer. The electrical solve uses filled polygons, tracks, actual pad shapes, plated connections and drilled voids, not just zone boundaries. Floating electrical components are unexcited. Model input, DRC, area parity, source code and numerical outputs accompany this report.
Electrical model and numerical checks
Four coupled copper sheets. Design-file copper thicknesses: outer 35 µm, inner 15.2 µm. Copper resistivity is an explicit nominal assumption of 1.724e-8 Ωm at 20°C. Via-barrel plating is unconfirmed; nominal 25 µm with 15/35 µm sensitivity. Contacts are ideal equipotential front-pad surfaces. Package, solder, connector and contact resistance are excluded. Plated barrels connect adjacent copper layers using the design-file spacing. No independent current source is assigned to floating copper.
The resistor grid rejects neighbor edges crossing an actual void or isolation gap. Nevertheless, boundary stair-stepping and partial cells cause mesh error. A 10 × 2 mm, 35 µm rectangular conductor gives 2.462857 mΩ, matching the analytic resistance to 2.5e-13 relative error. Source/sink current and dissipated-power checks pass; see JSON for each residual. This checks the numerical stencil, not fabrication or the entire physical model.
| Path | 0.10 mm mesh, mΩ | 0.15 mm mesh, mΩ | Change |
|---|---|---|---|
| vbat-Q1 | 12.979 | 13.765 | 5.7% |
| vbat-Q3 | 7.000 | 7.646 | 8.4% |
| vbat-Q5 | 0.509 | 0.508 | 0.2% |
| return-Q2 | 1.723 | 1.750 | 1.5% |
| return-Q4 | 1.845 | 1.879 | 1.8% |
| return-Q6 | 1.359 | 1.377 | 1.3% |
| battery-return | 0.128 | 0.134 | 4.5% |
| phase-A-high | 0.340 | 0.342 | 0.8% |
| phase-A-low | 0.341 | 0.347 | 1.7% |
| phase-B-high | 0.416 | 0.410 | 1.2% |
| phase-B-low | 0.355 | 0.361 | 1.8% |
| phase-C-high | 0.311 | 0.319 | 2.4% |
| phase-C-low | 0.308 | 0.311 | 1.1% |
For the critical +VBAT paths, further refinement from 0.10 to 0.075 mm changes Q1 resistance by 0.93%, Q3 by 3.07%, and Q5 by 0.57%. These are mesh comparisons, not confidence intervals. Narrow-neck peak current density is not qualified by this mesh.
| Assumed barrel plating, µm | Q1 feed mΩ | Q3 feed mΩ | Q5 feed mΩ |
|---|---|---|---|
| 15 | 14.467 | 7.518 | 0.536 |
| 25 | 12.859 | 6.785 | 0.506 |
| 35 | 12.145 | 6.450 | 0.491 |
The failure is robust to these tested plating assumptions. Increasing plating alone does not repair the topology. Copper resistivity also increases as it heats; cold loss estimates do not include that feedback.
A defined operating case, not an invented motor rating
The source design mentions a 58.5 A motor figure but does not establish whether this is battery average, line plateau or phase RMS, nor its duration. The following screening case is balanced six-step operation at unity PWM duty, two conducting FETs at a time, constant line-current magnitude, each high-side and each low-side active one third of the electrical cycle. This makes the averaging explicit. Other modulation/duty conditions require different RMS currents and local capacitor source paths.
Using the 0.10 mm full-board solve, average PCB copper loss is 0.00929023 × I² W. The MOSFET cold conduction term uses 1.6 mΩ per conducting device at the datasheet's 10 V gate/25°C condition; the shunt uses its nominal 0.5 mΩ. The PCB and device reference temperatures therefore differ slightly. Infineon datasheet
| Line plateau A | PCB copper W | MOSFET conduction W | Shunt W | Included total W |
|---|---|---|---|---|
| 10 | 0.93 | 0.32 | 0.05 | 1.30 |
| 15 | 2.09 | 0.72 | 0.11 | 2.92 |
| 20 | 3.72 | 1.28 | 0.20 | 5.20 |
| 30 | 8.36 | 2.88 | 0.45 | 11.69 |
| 40 | 14.86 | 5.12 | 0.80 | 20.78 |
| 58.5 | 31.79 | 10.95 | 1.71 | 44.46 |
The 58.5 A case therefore has about 44.5 W of included losses before switching, dead-time/recovery, capacitor ESR, auxiliary circuits and contact losses. This is an engineering rejection of the high-current case on the present layout, not a precise prediction of equilibrium temperature.
Thermal sensitivity, with limits exposed
A separate four-sheet finite-volume thermal screen includes the native copper area fractions, FR4 conduction and plated barrel conduction. Explicit provisional conductivities are 400 W/mK copper and 0.3 W/mK FR4; these are not measured laminate properties. The 64 × 74 mm rectangular outline approximates the rounded board. Both exterior faces have a uniform film coefficient; edges are adiabatic, and no heatsink/contact cooling is modeled. Coefficients below are sensitivity inputs, not verified mappings to fan speed or natural convection. Radiation is not modeled separately. Package bodies, enclosure, solder interfaces and detailed anisotropy are omitted.
Heat consists only of the balanced cold conduction losses above. MOSFET losses enter drain-pad cells; shunt heat is split between its pads. The model has no temperature feedback or heat capacity, so it does not establish burst duration. Copper sampling and the thermal mesh can blur sub-cell necks. Native drilled voids are respected in the electrical solve; the thermal screen homogenizes local copper/FR4 and does not resolve every hole-wall boundary. Uniform-temperature and total energy-balance numerical checks pass, but there is no measured thermal correlation.
| Film coefficient W/m²K, each face | Estimated hottest-board rise at 10 A, K | At 15 A, K | At 20 A, K | Peak change, 0.50 to 0.25 mm mesh |
|---|---|---|---|---|
| 5 | 41.2 | 92.8 | 165.0 | 5.2% |
| 10 | 27.0 | 60.7 | 107.9 | 7.9% |
| 25 | 17.6 | 39.6 | 70.4 | 12.0% |
| 50 | 13.8 | 31.0 | 55.0 | 15.0% |
These are screening estimates, not rated currents or measured temperatures. Hotspot maxima are still mesh-sensitive; do not quote them as precise local temperatures. The colder-loss assumption becomes increasingly inappropriate with increasing rise. The JSON also records a simplified junction-over-drain-pad calculation, but that is not a validated junction-temperature prediction. Datasheet thermal resistance from its reference PCB cannot simply be applied to this shared-copper board. Infineon thermal test conditions
Additional electrical and thermal gates
- Gate supply U1: ZXTR2012Z's nominal 30 mA description is not a hard maximum-current limit. Its safe operating area, input-output voltage drop and local thermal path must be checked together. Regulation is specified from 15 V input; the stated 3S range therefore needs dropout review. Diodes datasheet
- Gate/PWM loss: Gate charge, which gates switch each cycle, PWM frequency, actual rise/fall times and dead time are not established by the layout. Measure VGS/VDS and supply current. DRV8300 operating limits and local decoupling must be verified against the populated circuit. TI DRV8300 datasheet
- Shunt R32: 58.5 A produces 1.71 W at nominal 0.5 mΩ. The BOM's 3 W description alone does not establish mounted derating or pulse survival. Obtain the exact manufacturer's derating and overload curves; verify Kelvin measurements under load.
- DC-link C2/C3: The BOM lists two 330 µF/35 V capacitors, 30 mΩ ESR and 2.7 A ripple each at 100 kHz. Those are unverified BOM ratings for this review. Actual RMS ripple, frequency and temperature must be checked against exact manufacturer data. Do not equate motor current with capacitor ripple or assume perfect sharing.
- Auxiliary regulators: TPSM365R6 and AP2112 output-current descriptions do not guarantee operation at that current on this layout. Determine actual 5 V/3.3 V loads and losses. TI module, Diodes LDO
- Interfaces and fabrication: Verify contact ampacity, solder assembly, minimum copper/plating, the U2 land pattern and the 3rd party fab clearance capability. The inherited DRC errors remain a release blocker independently of this power-path finding.
Concrete corrective pass
- Rebuild the +VBAT distribution to provide a broad, continuous feed to all three high-side drains. The present filled regions narrow and change layers around the inter-phase bands, approximately y=83-92 mm and y=98-104 mm, near x=148-156 mm. The unit-current loss map identifies these as investigation regions, not exact neck-width measurements.
- Identify each signal cutting those regions before moving it. Move suitable gate/control traces into a deliberate corridor or short layer detour while preserving gate-source returns, Kelvin isolation and the commutation loop. Do not simply flood switching nodes or sacrifice the ground reference plane.
- Where current must change layers, provide an appropriately sized via array and broad copper attachment. Preserve insulation and all-layer antipad effects. Larger remote islands without better connections will not fix the resistance.
- Refill, run native DRC/connectivity, and compare the same source/sink resistance and loss cases before accepting a candidate. Check the return-to-shunt path as well. No new route or pour revision is claimed in this review.
- Select final current, voltage, duty/PWM, ambient, enclosure, airflow and temperature limits. Only then approve a candidate for the physical qualification matrix below.
Physical qualification matrix still required
Use a current-limited source and a controlled motor/dynamometer or suitable three-phase load. Measure four-wire voltage drops from MC1 to each high-side drain, each phase terminal, low-side sources to R32, and R32 to MC3. Compare cold resistance with the model, then hot resistance after stabilization. Instrument all six MOSFET regions, the two feed constrictions, shunt, gate regulator, capacitors and auxiliary regulators with appropriate calibrated temperature measurements. Case or infrared surface temperature alone is not junction temperature.
Sweep the agreed bus-voltage range, load and modulation at worst specified ambient/cooling. Check switching overshoot, gate ringing, shoot-through/dead time, current-sense integrity and capacitor ripple with suitable probes. Stop on the defined device, board or connector limits. Run the specified peak-current durations only after the steady-state case is understood; inspect permanent resistance drift and damage afterward. Acceptance needs measured limits plus margin, not just survival of one run. None of these hardware tests has been performed.
Reproduction and provenance
Python implements the electrical and thermal models; Shapely constructs native copper geometry, SciPy solves sparse systems, PyAMG preconditions them, and Matplotlib renders the loss map. This example is board-specific in terminals, geometry and operating assumptions. The general review method lives in the existing EDA Skillpack. Source is readable by any AI and should not be mistaken for a validated universal autorouter or thermal solver.
See source and numerical evidence. The analysis is a follow-up; it does not revise the original placement/routing timing or token benchmark. No AI subagents were spawned for this follow-up.
# Astra ESC G431 current and thermal qualification review
**Disposition: NOT QUALIFIED. The 58.5 A high-current screening case fails. No continuous or peak hardware current rating has been established.** This follow-up evaluates Astra's independent placement, routing and pours from [issue 96](https://wiki.adom.inc/adom/kicad-bridge/issues/96). It does not substitute Fable's placement or change the original layout/video benchmark.
The dominant finding is a poor +VBAT distribution path to Q1 and Q3. Large filled regions are connected through constricted copper and interlayer paths. A 0.075 mm electrical mesh gives **12.86 mΩ to Q1**, **6.79 mΩ to Q3**, and **0.506 mΩ to Q5** from input MC1.1. The Q1 path dissipates about **44.0 W while carrying 58.5 A** at the assumed cold copper resistivity. That is an instantaneous conducting-state stress calculation, not its balanced-cycle average and not a claim about actual motor current.
## Evidence and board identity
A separate native KiCad analysis copy was reconstructed from the recorded final segments, vias, placement and zone/keepout settings, then refilled on arav-rog. The original fixture was not saved or modified. Analysis copy SHA-256: `2ba0f80c7798d2ef37f5db37b2d849859149531efcc86125ae69e5a9b7b6ea32`. KiCad 10.0.3, kicad-bridge 1.0.7. Native result: **2079 segments, 246 vias, 21 zone objects; 0 unconnected, 13 errors and 63 warnings**. The 13 errors are the previously documented six Q1-Q6 malformed courtyards and seven U2 pad clearances. They remain unresolved manufacturing issues, not waived errors.
Native zone-filled areas reproduce the recorded result within 0.005 mm² per layer. The electrical solve uses filled polygons, tracks, actual pad shapes, plated connections and drilled voids, not just zone boundaries. Floating electrical components are unexcited. Model input, DRC, area parity, source code and numerical outputs accompany this report.
## Electrical model and numerical checks
Four coupled copper sheets. Design-file copper thicknesses: outer 35 µm, inner 15.2 µm. Copper resistivity is an explicit nominal assumption of 1.724e-8 Ωm at 20°C. Via-barrel plating is unconfirmed; nominal 25 µm with 15/35 µm sensitivity. Contacts are ideal equipotential front-pad surfaces. Package, solder, connector and contact resistance are excluded. Plated barrels connect adjacent copper layers using the design-file spacing. No independent current source is assigned to floating copper.
The resistor grid rejects neighbor edges crossing an actual void or isolation gap. Nevertheless, boundary stair-stepping and partial cells cause mesh error. A 10 × 2 mm, 35 µm rectangular conductor gives 2.462857 mΩ, matching the analytic resistance to 2.5e-13 relative error. Source/sink current and dissipated-power checks pass; see JSON for each residual. This checks the numerical stencil, not fabrication or the entire physical model.
| Path | 0.10 mm mesh, mΩ | 0.15 mm mesh, mΩ | Change |
|---|---:|---:|---:|
| vbat-Q1 | 12.979 | 13.765 | 5.7% |
| vbat-Q3 | 7.000 | 7.646 | 8.4% |
| vbat-Q5 | 0.509 | 0.508 | 0.2% |
| return-Q2 | 1.723 | 1.750 | 1.5% |
| return-Q4 | 1.845 | 1.879 | 1.8% |
| return-Q6 | 1.359 | 1.377 | 1.3% |
| battery-return | 0.128 | 0.134 | 4.5% |
| phase-A-high | 0.340 | 0.342 | 0.8% |
| phase-A-low | 0.341 | 0.347 | 1.7% |
| phase-B-high | 0.416 | 0.410 | 1.2% |
| phase-B-low | 0.355 | 0.361 | 1.8% |
| phase-C-high | 0.311 | 0.319 | 2.4% |
| phase-C-low | 0.308 | 0.311 | 1.1% |
For the critical +VBAT paths, further refinement from 0.10 to 0.075 mm changes Q1 resistance by 0.93%, Q3 by 3.07%, and Q5 by 0.57%. These are mesh comparisons, not confidence intervals. Narrow-neck peak current density is not qualified by this mesh.
| Assumed barrel plating, µm | Q1 feed mΩ | Q3 feed mΩ | Q5 feed mΩ |
|---|---:|---:|---:|
| 15 | 14.467 | 7.518 | 0.536 |
| 25 | 12.859 | 6.785 | 0.506 |
| 35 | 12.145 | 6.450 | 0.491 |
The failure is robust to these tested plating assumptions. Increasing plating alone does not repair the topology. Copper resistivity also increases as it heats; cold loss estimates do not include that feedback.
## A defined operating case, not an invented motor rating
The source design mentions a 58.5 A motor figure but does not establish whether this is battery average, line plateau or phase RMS, nor its duration. The following screening case is **balanced six-step operation at unity PWM duty**, two conducting FETs at a time, constant line-current magnitude, each high-side and each low-side active one third of the electrical cycle. This makes the averaging explicit. Other modulation/duty conditions require different RMS currents and local capacitor source paths.
Using the 0.10 mm full-board solve, average PCB copper loss is 0.00929023 × I² W. The MOSFET cold conduction term uses 1.6 mΩ per conducting device at the datasheet's 10 V gate/25°C condition; the shunt uses its nominal 0.5 mΩ. The PCB and device reference temperatures therefore differ slightly. [Infineon datasheet](https://www.infineon.com/assets/row/public/documents/24/49/infineon-bsc016n06ns-datasheet-en.pdf)
| Line plateau A | PCB copper W | MOSFET conduction W | Shunt W | Included total W |
|---|---:|---:|---:|---:|
| 10 | 0.93 | 0.32 | 0.05 | 1.30 |
| 15 | 2.09 | 0.72 | 0.11 | 2.92 |
| 20 | 3.72 | 1.28 | 0.20 | 5.20 |
| 30 | 8.36 | 2.88 | 0.45 | 11.69 |
| 40 | 14.86 | 5.12 | 0.80 | 20.78 |
| 58.5 | 31.79 | 10.95 | 1.71 | 44.46 |
The 58.5 A case therefore has about **44.5 W of included losses before switching, dead-time/recovery, capacitor ESR, auxiliary circuits and contact losses**. This is an engineering rejection of the high-current case on the present layout, not a precise prediction of equilibrium temperature.
## Thermal sensitivity, with limits exposed
A separate four-sheet finite-volume thermal screen includes the native copper area fractions, FR4 conduction and plated barrel conduction. Explicit provisional conductivities are 400 W/mK copper and 0.3 W/mK FR4; these are not measured laminate properties. The 64 × 74 mm rectangular outline approximates the rounded board. Both exterior faces have a uniform film coefficient; edges are adiabatic, and no heatsink/contact cooling is modeled. Coefficients below are sensitivity inputs, **not verified mappings to fan speed or natural convection**. Radiation is not modeled separately. Package bodies, enclosure, solder interfaces and detailed anisotropy are omitted.
Heat consists only of the balanced cold conduction losses above. MOSFET losses enter drain-pad cells; shunt heat is split between its pads. The model has no temperature feedback or heat capacity, so it does not establish burst duration. Copper sampling and the thermal mesh can blur sub-cell necks. Native drilled voids are respected in the electrical solve; the thermal screen homogenizes local copper/FR4 and does not resolve every hole-wall boundary. Uniform-temperature and total energy-balance numerical checks pass, but there is no measured thermal correlation.
| Film coefficient W/m²K, each face | Estimated hottest-board rise at 10 A, K | At 15 A, K | At 20 A, K | Peak change, 0.50 to 0.25 mm mesh |
|---|---:|---:|---:|---:|
| 5 | 41.2 | 92.8 | 165.0 | 5.2% |
| 10 | 27.0 | 60.7 | 107.9 | 7.9% |
| 25 | 17.6 | 39.6 | 70.4 | 12.0% |
| 50 | 13.8 | 31.0 | 55.0 | 15.0% |
**These are screening estimates, not rated currents or measured temperatures.** Hotspot maxima are still mesh-sensitive; do not quote them as precise local temperatures. The colder-loss assumption becomes increasingly inappropriate with increasing rise. The JSON also records a simplified junction-over-drain-pad calculation, but that is not a validated junction-temperature prediction. Datasheet thermal resistance from its reference PCB cannot simply be applied to this shared-copper board. [Infineon thermal test conditions](https://www.infineon.com/assets/row/public/documents/24/49/infineon-bsc016n06ns-datasheet-en.pdf)
## Additional electrical and thermal gates
- **Gate supply U1:** ZXTR2012Z's nominal 30 mA description is not a hard maximum-current limit. Its safe operating area, input-output voltage drop and local thermal path must be checked together. Regulation is specified from 15 V input; the stated 3S range therefore needs dropout review. [Diodes datasheet](https://www.diodes.com/datasheet/download/ZXTR2012Z.pdf)
- **Gate/PWM loss:** Gate charge, which gates switch each cycle, PWM frequency, actual rise/fall times and dead time are not established by the layout. Measure VGS/VDS and supply current. DRV8300 operating limits and local decoupling must be verified against the populated circuit. [TI DRV8300 datasheet](https://www.ti.com/lit/ds/symlink/drv8300.pdf)
- **Shunt R32:** 58.5 A produces 1.71 W at nominal 0.5 mΩ. The BOM's 3 W description alone does not establish mounted derating or pulse survival. Obtain the exact manufacturer's derating and overload curves; verify Kelvin measurements under load.
- **DC-link C2/C3:** The BOM lists two 330 µF/35 V capacitors, 30 mΩ ESR and 2.7 A ripple each at 100 kHz. Those are unverified BOM ratings for this review. Actual RMS ripple, frequency and temperature must be checked against exact manufacturer data. Do not equate motor current with capacitor ripple or assume perfect sharing.
- **Auxiliary regulators:** TPSM365R6 and AP2112 output-current descriptions do not guarantee operation at that current on this layout. Determine actual 5 V/3.3 V loads and losses. [TI module](https://www.ti.com/product/TPSM365R6), [Diodes LDO](https://www.diodes.com/datasheet/download/AP2112.pdf)
- **Interfaces and fabrication:** Verify contact ampacity, solder assembly, minimum copper/plating, the U2 land pattern and the 3rd party fab clearance capability. The inherited DRC errors remain a release blocker independently of this power-path finding.
## Concrete corrective pass
1. Rebuild the +VBAT distribution to provide a broad, continuous feed to all three high-side drains. The present filled regions narrow and change layers around the inter-phase bands, approximately y=83-92 mm and y=98-104 mm, near x=148-156 mm. The unit-current loss map identifies these as investigation regions, not exact neck-width measurements.
2. Identify each signal cutting those regions before moving it. Move suitable gate/control traces into a deliberate corridor or short layer detour while preserving gate-source returns, Kelvin isolation and the commutation loop. Do not simply flood switching nodes or sacrifice the ground reference plane.
3. Where current must change layers, provide an appropriately sized via array and broad copper attachment. Preserve insulation and all-layer antipad effects. Larger remote islands without better connections will not fix the resistance.
4. Refill, run native DRC/connectivity, and compare the same source/sink resistance and loss cases before accepting a candidate. Check the return-to-shunt path as well. No new route or pour revision is claimed in this review.
5. Select final current, voltage, duty/PWM, ambient, enclosure, airflow and temperature limits. Only then approve a candidate for the physical qualification matrix below.
## Physical qualification matrix still required
Use a current-limited source and a controlled motor/dynamometer or suitable three-phase load. Measure four-wire voltage drops from MC1 to each high-side drain, each phase terminal, low-side sources to R32, and R32 to MC3. Compare cold resistance with the model, then hot resistance after stabilization. Instrument all six MOSFET regions, the two feed constrictions, shunt, gate regulator, capacitors and auxiliary regulators with appropriate calibrated temperature measurements. Case or infrared surface temperature alone is not junction temperature.
Sweep the agreed bus-voltage range, load and modulation at worst specified ambient/cooling. Check switching overshoot, gate ringing, shoot-through/dead time, current-sense integrity and capacitor ripple with suitable probes. Stop on the defined device, board or connector limits. Run the specified peak-current durations only after the steady-state case is understood; inspect permanent resistance drift and damage afterward. Acceptance needs measured limits plus margin, not just survival of one run. **None of these hardware tests has been performed.**
## Reproduction and provenance
Python implements the electrical and thermal models; Shapely constructs native copper geometry, SciPy solves sparse systems, PyAMG preconditions them, and Matplotlib renders the loss map. This example is board-specific in terminals, geometry and operating assumptions. The general review method lives in the existing EDA Skillpack. Source is readable by any AI and should not be mistaken for a validated universal autorouter or thermal solver.
See [source and numerical evidence](https://wiki.adom.inc/adom/eda-engineering/files/docs/examples/astra-esc-independent/thermal/README.md). The analysis is a follow-up; it does not revise the original placement/routing timing or token benchmark. No AI subagents were spawned for this follow-up.