Codex

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" />
 <param name="dpMaxLengthDifference" value="10mm" />
 <param name="dpGapFactor" value="2.5" />
-<description language="en">Adom InstaPCB 4-Layer design rules
+<description language="en">3rd party fab 4-Layer design rules
 
 Board thickness: 1.6mm
 Copper weight: 1oz (35um)
@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)
 
 Vias:
-- Min 0.15mm via allowed on 4-layer now with InstaPCB
-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred
+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab
+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred
 Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter
 
 Drill:
@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.
 
 Annular Ring:
-Vias: 0.1mm annular ring is InstaPCB min
-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min
+Vias: 0.1mm annular ring is the 3rd party fab min
+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min
 However, they prefer 0.25mm annular ring or above
 
 </description>

@@ -1694,7 +1694,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm" />
 <param name="dpMaxLengthDifference" value="10mm" />
 <param name="dpGapFactor" value="2.5" />
-<description language="en">Adom InstaPCB 4-Layer design rules
+<description language="en">3rd party fab 4-Layer design rules
 
 Board thickness: 1.6mm
 Copper weight: 1oz (35um)
@@ -1713,8 +1713,8 @@ Min. track width and spacing (1 oz) 0.10 / 0.10 mm (4 / 4 mil)
 
 Vias:
-- Min 0.15mm via allowed on 4-layer now with InstaPCB
-- We made preferred 0.25mm, although InstaPCB says 0.2 is preferred
+- Min 0.15mm via allowed on 4-layer now with the 3rd party fab
+- We made preferred 0.25mm, although the 3rd party fab says 0.2 is preferred
 Min. Via hole size/diameter 4-layer: 0.15mm hole size / 0.25mm via diameter
 
 Drill:
@@ -1723,8 +1723,8 @@ Min. Non-plated holes - 0.50mm Holes with diameter ≥ 6.3 mm are CNC routed from a smaller drilled hole.
 
 Annular Ring:
-Vias: 0.1mm annular ring is InstaPCB min
-Pads (through-hole parts): 0.18mm annular ring is InstaPCB min
+Vias: 0.1mm annular ring is the 3rd party fab min
+Pads (through-hole parts): 0.18mm annular ring is the 3rd party fab min
 However, they prefer 0.25mm annular ring or above
 
 </description>

@@ -29,7 +29,7 @@ The [baseline](https://wiki.adom.inc/api/pages/adom/codex/files/docs/astra-esc-i  ## Electrical decisions and limits -Signal routing uses 0.25 mm with 0.2 mm clearance and 0.8/0.4 mm vias. Power routes use 0.5 mm and widen to 1.0 mm where clearance permits. Compact phase regions cover the half-bridge and contact, rather than spreading switching copper across the signal area. Broad supply and ground regions retain copper for InstaPCB. Local solid connections address high-current pads and five starved thermal connections; other pads retain thermal reliefs.+Signal routing uses 0.25 mm with 0.2 mm clearance and 0.8/0.4 mm vias. Power routes use 0.5 mm and widen to 1.0 mm where clearance permits. Compact phase regions cover the half-bridge and contact, rather than spreading switching copper across the signal area. Broad supply and ground regions retain copper for the 3rd party fab. Local solid connections address high-current pads and five starved thermal connections; other pads retain thermal reliefs.  The two Kelvin traces were routed first and protected from same-net copper. U6.3 has no generic GND plane stub. The final review found that a centerline keepout left 0.475573 mm² of each sense-input pad exposed; added pad-shape keepouts corrected this. [Geometry audit](https://wiki.adom.inc/api/pages/adom/codex/files/docs/astra-esc-independent/kelvin-geometry-audit.json) shows zero uncovered input-pad/trace area and zero contact with other same-net trace/via/pad copper outside the intended shunt pickup. The API does not expose filled polygon vertices, so this is not a direct polygon-union measurement of the native fills. 

@@ -83,7 +83,7 @@ Heat consists only of the balanced cold conduction losses above. MOSFET losses e - **Shunt R32:** 58.5 A produces 1.71 W at nominal 0.5 mΩ. The BOM's 3 W description alone does not establish mounted derating or pulse survival. Obtain the exact manufacturer's derating and overload curves; verify Kelvin measurements under load. - **DC-link C2/C3:** The BOM lists two 330 µF/35 V capacitors, 30 mΩ ESR and 2.7 A ripple each at 100 kHz. Those are unverified BOM ratings for this review. Actual RMS ripple, frequency and temperature must be checked against exact manufacturer data. Do not equate motor current with capacitor ripple or assume perfect sharing. - **Auxiliary regulators:** TPSM365R6 and AP2112 output-current descriptions do not guarantee operation at that current on this layout. Determine actual 5 V/3.3 V loads and losses. [TI module](https://www.ti.com/product/TPSM365R6), [Diodes LDO](https://www.diodes.com/datasheet/download/AP2112.pdf)-- **Interfaces and fabrication:** Verify contact ampacity, solder assembly, minimum copper/plating, the U2 land pattern and InstaPCB clearance capability. The inherited DRC errors remain a release blocker independently of this power-path finding.+- **Interfaces and fabrication:** Verify contact ampacity, solder assembly, minimum copper/plating, the U2 land pattern and the 3rd party fab clearance capability. The inherited DRC errors remain a release blocker independently of this power-path finding.  ## Concrete corrective pass 

@@ -14,11 +14,11 @@ The BQ25792 comparison disables one inherited all-object same-net spacing rule o  ## Earlier team overview: released routing, verified checks -This newly narrated short reel follows the progression from simple routing to the BQ25792 board, retained copper, thermal planning, expanded pours and bottleneck rerouting. Historical native Fusion footage retains its 10× action labels and inspection holds. The updated ending reflects the independent release checks: six-net per-trace routing completed in 55.1 seconds on 1.10.2; the saved fixture then passed the corrected, unmodified InstaPCB 2L profile with zero errors, warnings or airwires on 1.10.5, and explicit net highlighting was visually verified.+This newly narrated short reel follows the progression from simple routing to the BQ25792 board, retained copper, thermal planning, expanded pours and bottleneck rerouting. Historical native Fusion footage retains its 10× action labels and inspection holds. The updated ending reflects the independent release checks: six-net per-trace routing completed in 55.1 seconds on 1.10.2; the saved fixture then passed the corrected, unmodified 3rd party fab 2L profile with zero errors, warnings or airwires on 1.10.5, and explicit net highlighting was visually verified.  <video width="100%" controls playsinline preload="metadata" src="https://wiki.adom.inc/api/pages/adom/codex/files/videos/fusion/00-fusion-astra-team-final.mp4"></video> -These fixture checks do not certify the full BQ design, thermal power ratings or automatic Hydrogen prompt delivery. General routing and copper-engineering skills belong to Fusion Bridge; the worked boards and recording scripts are optional examples. Select Codex and Astra in Hydrogen and manually paste the [reproduction prompt](https://wiki.adom.inc/adom/codex/files/docs/REPRODUCE-FUSION.md). [Highlight fix and retest](https://wiki.adom.inc/adom/fusion-bridge/issues/81) · [InstaPCB rule fix and retest](https://wiki.adom.inc/adom/fusion-bridge/issues/82).+These fixture checks do not certify the full BQ design, thermal power ratings or automatic Hydrogen prompt delivery. General routing and copper-engineering skills belong to Fusion Bridge; the worked boards and recording scripts are optional examples. Select Codex and Astra in Hydrogen and manually paste the [reproduction prompt](https://wiki.adom.inc/adom/codex/files/docs/REPRODUCE-FUSION.md). [Highlight fix and retest](https://wiki.adom.inc/adom/fusion-bridge/issues/81) · [3rd party fab rule fix and retest](https://wiki.adom.inc/adom/fusion-bridge/issues/82).  ## Earlier two-minute progression overview @@ -38,7 +38,7 @@ Astra revisits the expanded copper and moves selected N$1, VUSB and ground route  **3:11, narrated.** Three-times-speed native action, edited waits and inspection holds, followed by calculated comparisons. Under the same illustrative fixed-temperature model, VAC1 gains about **33% calculated bottom heat flow** with only about 2.8% more connected area. This is a model comparison, not measured cooling or a board power rating. -The replay has **583 segments, 89 vias, 12 pours, zero airwires and zero new DRC errors under the prior diagnostic profile**; one inherited error remains. It is not a demonstration of passing the unmodified InstaPCB manufacturing profile. The manual/automatic new-user acceptance tests and the shared skillpack release remain separate work.+The replay has **583 segments, 89 vias, 12 pours, zero airwires and zero new DRC errors under the prior diagnostic profile**; one inherited error remains. It is not a demonstration of passing the unmodified 3rd party fab manufacturing profile. The manual/automatic new-user acceptance tests and the shared skillpack release remain separate work.  [Analysis, tradeoffs and board downloads](FUSION-THERMAL-BOTTLENECKS.md) · [Download video 12](https://wiki.adom.inc/api/pages/adom/codex/files/videos/fusion/12-bq25792-thermal-bottlenecks-narrated.mp4) 

@@ -30,7 +30,7 @@ This is a concrete demonstration of independent placement, not a declaration tha | Wire direction | Horizontal, vertical or 45° within coordinate quantization tolerance | | Molecule grid | 53 machine-pin pad centers checked; zero off-grid failures | | Native DRC after refill and final repair | **0 airwires, 0 errors, 0 warnings** |-| Rule profile | InstaPCB 4L with requested 0.1 mm isolation floor; stricter 0.15 mm pad-to-pad and 0.2 mm edge/drill spacing retained |+| Rule profile | 3rd party fab 4L with requested 0.1 mm isolation floor; stricter 0.15 mm pad-to-pad and 0.2 mm edge/drill spacing retained | | Final movie | 1920 × 1080, H.264/AAC, 252.02 seconds; complete decode passed |  The reference under the same profile reported 14 wire-stub errors and seven warnings; it is preserved as a separate baseline. Medium-contact drills were explicitly updated from 0.84 mm to the current component definition's 0.78 mm. Press-fit validation is still needed.

@@ -9,7 +9,7 @@     "In2.Cu": 0.0152,     "B.Cu": 0.035   },-  "manufacturer": "Adom InstaPCB",+  "manufacturer": "3rd party fab",   "signalWidthMm": 0.25,   "clearanceMm": 0.2,   "viaDiameterMm": 0.8,

@@ -13,7 +13,7 @@ The original Adonis board is preserved in the public `adom/bq25792-charger` sour - Medium-contact footprint drills updated from the source's 0.84 mm to the current component definition's 0.78 mm. This is an explicit footprint change, not an unnoticed difference. - Final native geometry: 879 wire segments, 157 routing vias, 69 pour outlines. All wire segments horizontal, vertical or 45 degrees within coordinate quantization tolerance. - Final native DRC: **0 airwires, 0 errors, 0 warnings**. Evidence: `join-repair-recording/final-drc.json`.-- Active saved profile: `InstaPCB 4L with John 0.1mm isolation floor`. Different-net copper clearances retain the floor; pad-to-pad remains the stricter 0.15 mm, copper-to-edge 0.2 mm and drill-to-drill 0.2 mm.+- Active saved profile: `3rd party fab 4L with John 0.1mm isolation floor`. Different-net copper clearances retain the floor; pad-to-pad remains the stricter 0.15 mm, copper-to-edge 0.2 mm and drill-to-drill 0.2 mm. - Final copper coverage, via identities, pour outlines/properties and placement audited against the accepted calculation plus the recorded explicit LDO_3V3 join: `final-audit.json`. - Both C32/PMID and C18/SYS and their PGND returns reach IC1 on connected top-layer copper in the native filled-geometry analysis. 

@@ -1632,7 +1632,7 @@ Used as a test point connection for pogo pins or other debugging tools. <class number="1" name="pwr" width="0.09" drill="0"> </class> </classes>-<designrules name="InstaPCB 4L with John 0.1mm isolation floor" version="V1">+<designrules name="3rd party fab 4L with John 0.1mm isolation floor" version="V1"> <rules> <rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>  <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>@@ -1695,7 +1695,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm"/> <param name="dpMaxLengthDifference" value="10mm"/> <param name="dpGapFactor" value="2.5"/>-<description language="en">Adom InstaPCB 4-layer design rules (standard process)+<description language="en">3rd party fab 4-layer design rules (standard process)  Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs

@@ -1633,7 +1633,7 @@ Used as a test point connection for pogo pins or other debugging tools. <class number="1" name="pwr" width="0.09" drill="0"> </class> </classes>-<designrules name="InstaPCB 4L with John 0.1mm isolation floor" version="V1">+<designrules name="3rd party fab 4L with John 0.1mm isolation floor" version="V1"> <rules> <rulecategory type="Copper Clearance" manualdrc="yes" livedrc="yes"/>  <rulecategory type="Keepout Clearance" manualdrc="yes" livedrc="yes"/>@@ -1696,7 +1696,7 @@ Used as a test point connection for pogo pins or other debugging tools. <param name="msDrill" value="0.15mm"/> <param name="dpMaxLengthDifference" value="10mm"/> <param name="dpGapFactor" value="2.5"/>-<description language="en">Adom InstaPCB 4-layer design rules (standard process)+<description language="en">3rd party fab 4-layer design rules (standard process)  Min trace width: 0.09 mm (3.54 mil) - 1 oz copper, multilayer Min spacing: 0.09 mm (3.54 mil) - 1 oz copper, multilayer, different nets; 3 mil acceptable in BGA fan-outs

@@ -4,7 +4,7 @@   "type": "app",   "title": "Codex",   "brief": "Codex in Adom Hydrogen: ecosystem setup, dock dashboard and live engineering demos.",-  "version": "0.1.25",+  "version": "0.1.26",   "description": "Codex in Adom Hydrogen with reusable CAD routing, electrical review, copper-ablation and narrated video skills, plus verified KiCad and Fusion demo progressions.",   "org": "adom",   "needs_sudo": false,

@@ -4,7 +4,7 @@   "type": "app",   "title": "Codex",   "brief": "Codex in Adom Hydrogen: ecosystem setup, dock dashboard and live engineering demos.",-  "version": "0.1.25",+  "version": "0.1.26",   "hero": {     "type": "image",     "path": "screenshots/hero.png"

@@ -8,9 +8,9 @@ Parent skill: codex-adom  Before routing or changing fabrication rules, check whether the user has already chosen a manufacturer and process in this conversation or the project requirements. Honor that choice without asking again. Otherwise, discover available profiles from `adom/pcb-design-rules` (or the selected bridge's rule-profile listing) and ask: -“Who would you like to manufacture this board? I can automatically load and verify the matching design rules—for example, InstaPCB, JLCPCB or PCBWay. You can also name another manufacturer or keep the current rules for now.”+“Who would you like to manufacture this board? I can automatically load and verify the matching design rules—for example, JLCPCB or PCBWay. You can also name another manufacturer or keep the current rules for now.” -Offer only manufacturers with available profiles as automatic-loading choices. Explain briefly that the choice affects trace widths, clearances, drills/vias and other fabrication limits. Do not silently default to InstaPCB or choose the smallest limits. If the user is undecided, retain and label the current rules as provisional; continue inspection while waiting, and defer manufacturer-dependent route generation or rule replacement until a choice is made.+Offer only manufacturers with available profiles as automatic-loading choices. Explain briefly that the choice affects trace widths, clearances, drills/vias and other fabrication limits. Do not silently default to the bundled 3rd party fab rules or choose the smallest limits. If the user is undecided, retain and label the current rules as provisional; continue inspection while waiting, and defer manufacturer-dependent route generation or rule replacement until a choice is made.  Once selected, resolve the profile for the actual layer count, process and copper assumptions. Ask a focused follow-up only if a missing process choice materially changes the rules. Load it through the selected CAD bridge, export/read back the active rules, and report the profile and meaningful limits before routing. Preserve stricter electrical and user constraints. If no compatible profile exists, explain what is missing and obtain a supplied or authoritative profile rather than inventing one. Switching manufacturers later requires revalidation of the existing board and may require rerouting.