Astra independent ESC placement, routing and pours

This is the independent Astra run from 13 September 2026. The input has 149 footprints: 122 parked movable parts and 27 locked interface contacts. Astra calculated new placement coordinates from that unplaced fixture, corrected the shunt orientation, calculated new traces, and committed them through the native KiCad Bridge. Fable placement coordinates and routes were not inputs. The model had seen this board previously; this is not a blind first encounter.

Final native result: 0 unconnected, 13 inherited errors (7 U2 pad clearances and 6 malformed MOSFET courtyards), 2079 segments, 246 vias, 1419.552 mm of track centerline. No new errors and no dangling-track warning. This is a connectivity and layout candidate, not a validated motor-current or thermal rating.

Video and full report.

What the source does

Python handles pad geometry, board-specific placement anchors and courtyard packing, connectivity groups, obstacle rasterization, rip-up scheduling, copper-pour polygons, native Bridge calls and evidence. search2.cpp and search3.cpp are C++ grid-search workers. The C++ algorithms and connected-component methods are reusable, but this directory is a worked board-specific implementation, not a drop-in general autorouter. Board bounds, functional anchors, power-net classifications, Kelvin pin assignments, layer policy and tolerances must be supplied and reviewed for a new board.

Astra wrote the fresh placement policy and routing orchestration, reused its own earlier geometry/search code, and calculated new routes. fixture_geometry.py is the shared KiCad Bridge fixture/parser utility, not a claim of original Astra authorship. Native KiCad checks every proposed commit and supplies the final DRC. No Freerouting was installed or run. No AI subagents were spawned; serial local C++ workers were used.

Reproduce analysis

Use Python 3 with NumPy and Shapely 2, and a C++17 compiler. Work in this directory. Compile g++ -O3 -std=c++17 search2.cpp -o search2 and g++ -O3 -std=c++17 search3.cpp -o search3. python3 fresh_place.py calculates the initial placement. Its initial R32 angle of 90 degrees is intentionally retained as experiment evidence; build_route_input.py applies the reviewed 270-degree correction. Do not describe reusing the supplied final plan as fresh planning.

route_fresh.py, pass2.py, repair_fresh.py and negotiate_fresh.py record the iterative routing approach. soft3-current.json is the accepted zero-gap candidate. widen_fresh.py produces live-routes.json, then audit_plan.py live-routes.json checks combined geometric clearance/connectivity. Inspect native board rules and footprint rule areas before adapting this planner. Geometry checks are not a substitute for native DRC.

Replay and review

bridge.py has this experiment's explicit desktop and disposable board path. Adapt both before use. Read the installed KiCad placement, routing and copper-pour skills, inspect current target/document/revision, and record before mutations. Replay the new placement, including R32=270, create the two reference planes, and read a settled revision before the next commit. land_routes.py expects the placed board with planes but no tracks/vias, and deliberately leaves the recorder active on success for pours. Do not run it as an unattended universal entry point.

The accepted outer-pours.json includes local thermal-relief repairs. stitching.json includes 40 via connections anchored to their intended pads. Via-only paths were rejected because native connectivity reassigned some isolated vias to inner planes. Add kelvin-pad-keepouts.json as well as the trace keepouts: covering the centerline alone left part of each sense-input pad exposed. Keepouts must cover the full pad/annulus and the whole sense route, except the intended shunt pickup.

trim_final.py documents the removal of one dangling +12V tail and its replacement with an explicit junction. Its UUID is specific to this live run; locate the corresponding geometry instead of reusing that UUID in another replay. Finish with native refill, DRC and readback. Never bypass a rejection. Preserve the untouched fixture and discard editor changes for this throwaway test.

Limits that matter

The routed copper is connected, but power zones still contain separate filled regions linked by traces/vias. Projected area does not prove adequate current sharing or cooling. The outer copper is 35 um and the inner copper about 15.2 um; the motor's 58.5 A figure is not a qualified PCB rating. Continuous/peak phase currents, duty, allowable temperature rise, enclosure and via plating remain necessary for power qualification. The search still generates many short grid segments; do not equate a zero-open result with optimal routing quality.

The public report preserves all stage times, real total elapsed time, retries, recorder interruption, token/cost estimate, per-net Bridge results and narration notes. Recorded stage playback is not a measure of planning time. The original fixture was never saved and its final SHA256 remained 78eff049795cff44552b3b80d65b43a44e81bdc8ab06a2af2e9a59fb7956e664.