TPS16850VMAR

Texas Instruments · 9 V to 80 V, 20 A integrated hot-swap eFuse · LQFN-CLIP-23 (VMA, 6.0 x 5.0 mm)

TPS16850VMAR is the auto-retry, 73 A fixed-fast-trip member of TI's TPS1685x family: an integrated eFuse with a 3.5 mOhm (typical) FET for 9 V to 80 V rails, an adjustable 2 A to 20 A circuit breaker with a transient timer, adjustable undervoltage and overvoltage thresholds, inrush (dVdT) control, a fast and accurate analog current monitor, an analog die-temperature output, and power-good and fault flags. Several devices can run in parallel with synchronised states and active current sharing (SLVSHA1D p.1).

Key specifications

Pinout (top view)

Source: SLVSHA1D Figure 5-1 and Table 5-1 (p.4 to p.5). Pins IN, OUT and NC repeat; the symbol shows every pin so each pad has its own pin.

Design notes

• Do not leave floating: ILIM, IMON, IREF, EN/UVLO and OVP; SFT_SEL is not recommended floating (p.4, p.5).
• Capacitance: TI's recommended operating conditions call for at least 10 nF on IN and 10 uF on OUT, and limit the hot-plug slew rate on IN to 100 V/us (p.7).
• Parallel operation: tie SWEN, TEMP and the current-sharing pins as TI describes for a primary and secondaries; MODE to GND makes a device a secondary (p.5).
• Layout: IN and OUT carry the load current through the combs (pins 7, 10, 22), pin 23 and the exposed pad; TI's land pattern puts 12 vias in the exposed pad (p.55).
• Family: TPS16850 (auto-retry, 73 A fast trip), TPS16851 (latch-off, 73 A), TPS16850A (auto-retry, 83 A), TPS16851A (latch-off, 83 A); all share this package and land pattern (p.3, p.50).

CAD

Library notes. adom-lbr 2.47.5 does not carry KiCad custom-pad shapes or paste-only pads, so the Fusion and Altium files are made from provenance/tps16850vmar-lbr-input.kicad_mod: the same copper with every L and comb pad written as a union of rectangles, and the copper under the solder mask as rectangles with mask and paste expansion -1.2 mm (no opening). Fixed by hand (provenance/tools/lbr_fix.py): the Fusion NC pins are typed nc (the tool wrote io), every pin shows its name, the fab outline is wires, and TI's six paste windows are on tCream. Altium has no no-connect pin type, so pins 11, 17 and 21 are Passive there; and because adom-lbr writes no paste-layer regions, the Altium exposed pad has one paste aperture with the area of TI's six windows (expansion -0.174 mm, 6.11 mm2): replace it with TI's windows if your assembler wants them.

Footprint

The pads follow TI's LAND PATTERN EXAMPLE and SOLDER PASTE EXAMPLE for VMA0023A (SLVSHA1D p.55 and p.56):

• signal pads 0.25 mm wide on a 0.5 mm pitch; pads 1 to 4 and 11 to 16 are 0.65 mm long, pad 5 is 0.70 mm, pads 18 to 21 are 0.60 mm and pads 8 and 9 are 0.75 mm; pad 23 is a 1.3 mm bar;
• pads 6 and 17 are L shapes; pads 7, 10 and 22 are solder-mask-defined combs on a larger copper rectangle (TI draws the metal under the mask dashed and the mask opening as a comb);
• the exposed pad (IN) is 3.4 x 2.35 mm, centred 0.075 mm above the package centre line, with TI's 12 vias (0.2 mm drill, tented) and six 0.98 x 1.04 mm paste windows (76 % coverage);
• plain pad corners R0.05 as TI prints them.

Drawn at TI's 15X scale on the datasheet page, the copper and the comb openings land on TI's strokes; pad by pad, every copper, mask and paste area agrees with TI's VMA0023A footprint as published through Ultra Librarian to within 0.05 mm2 (corner treatment). KiCad has no VMA0023A footprint to compare with. Details: provenance/footprint-check.json.

Heatsink vias

Pin 1

Pin 1 (ILIM) is on the left side, 0.5 mm above the package centre line in the top view; numbering runs counter-clockwise, and the exposed pad's 45 degree chamfer and TI's pin-1 index area are at the top-left corner (p.4, p.54). Footprint pad 1 is at (-2.875, -0.5) in KiCad's Y-down frame with a silkscreen dot to its left; the 3D model's pin-1 terminal sits on it with zero offset and rotation; the symbol's pin 1 is ILIM. TI's reel puts pin 1 in quadrant Q1 (p.52).

3D models

Frame for every file: Z up, seated on z = 0, centred on the footprint origin, X along the 6.0 mm side, pin 1 at (-x, +y).

How the model was made. TI's product page links its CAD models through Ultra Librarian, whose STEP download sits behind a reCAPTCHA form, so TI's STEP was not obtained, and KiCad has no model for this package. The model was therefore built by AI (Claude, for Adom) with CadQuery from TI's VMA0023A package outline (p.54) (provenance/tools/build_vma23.py): a 6.0 x 5.0 x 1.4 mm mould on a 0.025 mm stand-off, the 23 terminals and the exposed pad as drawn (combs, L shapes, rounded inner ends), 0.2 mm terminal exposure on the side walls. Colours follow TI's package render: dark grey mould, NiPdAu terminal faces, copper where the terminals are sawn through at the side walls. Drawn over TI's bottom view, 97 % of the model's edges land on TI's lines; the side view matches the terminal exposures (TI draws the body at its 1.5 mm maximum, the model is at the 1.4 mm nominal). Method and every dimension: provenance/3d-model.json.

The marking is virtual. The etch reads TPS16850 / VMAR, the orderable part number, so the part is identifiable in a 3D board view. TI's real marking is TPS16850 with lot trace information (p.50). The etch was made with adom-chip-laser (service-occt flat mark 5 um above the top face) placed by the adom-aiflow-etch planner from the footprint; its gate passes.

Detail levels for board and digital-twin viewers

All four share the library model's frame and carry no footprint, silkscreen or label artwork. High is the etched GLB; medium and low have square inner terminal ends (medium keeps the etch); super-low also drops the copper end slices. Every level keeps all terminals and the exposed pad. Status: candidate; the previews were inspected, a streaming LOD viewer has not qualified them.

Symbol chip outline

The symbol body carries the chip outline drawn from the etched model by adom-aiflow-etch outline (gate PASS): artwork/TPS16850VMAR-3d-outline-dark-named.svg. The KiCad symbol, the Fusion library and the Altium SchLib carry the same drawing.

Sourcing

Checked 2026-10-21 with adom-parts-search.

Manufacturer and resources

Provenance

• Datasheet: TI SLVSHA1D, 57 pages, sha256 fe9d96bfb8f8e13b, downloaded from ti.com on 2026-10-21 (docs/tps16850vmar-datasheet.pdf). Every pin and spec above cites its page.
• Footprint: provenance/footprint-check.json, pad by pad against p.55 and p.56 and against TI's Ultra Librarian footprint; built by build_fp.py on adom-footprint 1.0.26.
• 3D model: provenance/3d-model.json: source attempts, build, dimensions, overlay scores, etch gate, hashes. Tools in provenance/tools/.
• Symbol: created from provenance/tools/symbol-create.json by adom-symbol 1.2.6, then every pin moved onto the 2.54 mm grid by snap_symbol.py (the tool placed the first pin of each column at y = -2.00 and spaced groups 8.35 mm apart).
• Hero: adom/component-hero 0.1.2 hero_glb.py (adom-hero 1.4, align OK), then hero_post_vias.py adds the heatsink-via layer.
• Licence: Adom-authored files are CC-BY-4.0, see LICENSE. The datasheet and its page images are TI's and keep TI's terms.

Cited datasheet pages: