MCP2562FD-E/SN

Microchip Technology · High-speed CAN FD transceiver with VIO pin · SOIC-8 (SN, 3.90 mm body)

MCP2562FD-E/SN is the SOIC-8, extended-temperature member of Microchip's MCP2561/2FD family: a second-generation high-speed CAN transceiver that implements the ISO 11898-2 and ISO 11898-5 physical layer, guarantees loop delay symmetry for CAN FD, and has a VIO pin so TXD, RXD and STBY talk directly to 1.8 V to 5.5 V logic while the transceiver runs from a 5 V VDD (DS20005284B p.1, p.4).

Key specifications

Pinout (SOIC-8, top view)

Source: DS20005284B p.4 (Table 1-2) and p.5 (sections 1.7.1 to 1.7.9).

Design notes

• Two supplies. VDD needs 4.5 V to 5.5 V; VIO follows the controller's logic rail. The bus wake-up function needs both in range (p.3). Microchip's application figure decouples each with 0.1 uF (Figure 1-2, p.6).
• Modes. STBY low = Normal; STBY high = Standby, where RXD shows a filtered copy of the bus so a dominant bus can wake the controller (Table 1-1, p.3).
• Dominant time-out. A TXD or bus dominant for longer than 1.25 ms (typ) is treated as a fault, which limits the slowest usable bit time to 69.44 us (p.4).
• EMC. Microchip notes a common-mode choke may be needed above 1 Mbps (p.6). Example only: the typical-application figure ends the bus in 120 Ohm; split termination is drawn for the MCP2561FD's SPLIT pin, which this part does not have.
• Family. MCP2561FD has a SPLIT pin on pin 5 instead of VIO; MCP2562FDT-E/SN is this part on tape and reel; -H parts run to +150 C; the SNVAO suffix is AEC-Q100 qualified (p.29).

CAD

Footprint

The pads follow Microchip's recommended land pattern (DS20005284B p.25, drawing C04-02057-SN Rev L): eight 1.55 x 0.60 mm rectangles, contact pad spacing C = 5.40 mm (pad centres at x = +-2.70), pitch 1.27 mm. Each pad was compared with the drawing (provenance/footprint-check.json): all eight match.

KiCad's stock SOIC-8_3.9x4.9mm_P1.27mm is not the same pattern: its pads are 1.95 x 0.60 mm at x = +-2.475 (IPC nominal for JEDEC MS-012), reaching 0.425 mm further under the body. Either solders; this page follows the manufacturer.

Pin 1: pad 1 is top left in KiCad's footprint frame, with a silkscreen bar above it. The 3D model's pin 1 lead and its pin-1 dimple land on pad 1 with zero offset and rotation, and the pin order runs counter-clockwise seen from the top, as in Microchip's top view (p.23).

3D models

Frame for every file: Z up, seated on z = 0, centred on the footprint origin, pin 1 at (-x, +y), which is footprint pad 1.

How the model was made. Microchip's product page links its CAD models, but the page refused a plain request, so the manufacturer STEP was not obtained. KiCad's library model SOIC-8_3.9x4.9mm_P1.27mm.step was measured against Microchip's SN drawing (C04-00057-SN Rev L, p.24): every dimension fits except the foot. Measured on a section through pin 1's centre line, from the lead tip to where the lead's lower surface crosses the 0.25 mm gauge plane (JEDEC), KiCad's foot is 0.362 mm; Microchip's minimum is 0.40 mm (0.275 mm flat on KiCad's model). So the model was built from the drawing with CadQuery (provenance/tools/build_soic8.py), keeping KiCad's radiused gull-wing bends, lead angle, mold draft and pin-1 dimple and lengthening the flat foot until the gauge-plane foot measures 0.500 mm. Method and both numbers are in provenance/3d-model.json.

Not modelled: the optional end chamfer h.

The marking is virtual. The etch reads MCP2562 / FD-E/SN, the orderable part number, so the part is identifiable in a 3D board view. Microchip's real marking is 2562FDE / SN e3 YYWW / NNN (p.17). The etch was made with adom-chip-laser (service-occt flat mark, 5 um above the top face) placed by the adom-aiflow-etch planner from the footprint; its gate passes (axis, upright with pin 1 lower left, size 0.47 mm caps, band, flat, group, colour, widget).

Detail levels for board and digital-twin viewers

All four share the library model's frame and carry no footprint, silkscreen or label artwork. High is the etched GLB; medium and low come from the same generator with each bend drawn as three straight segments (medium keeps the etch); super-low has an undrafted body and one-segment bends. Every level keeps the eight leads and the pin-1 dimple. Status: candidate; the previews were inspected, a streaming LOD viewer has not qualified them.

Symbol chip outline

The symbol body carries the chip outline drawn from the etched model by adom-aiflow-etch outline (gate PASS): artwork/MCP2562FD-E-SN-3d-outline-dark-named.svg. The KiCad symbol, the Fusion library and the Altium SchLib carry the same drawing.

Sourcing

Checked 2026-10-21 with adom-parts-search.

The -E/SN part ships in tubes; order MCP2562FDT-E/SN for tape and reel (p.29).

Manufacturer and resources

Related

• adom/mcp2562fdt-e: an earlier page for the tape-and-reel ordering code, built on KiCad's generic footprint and model.
• adom/mcp2562t-e: the classical-CAN MCP2562.

Provenance

• Datasheet: Microchip DS20005284B (March 2026), 31 pages, sha256 659565909388fcd7, downloaded from microchip.com on 2026-10-21 (docs/mcp2562fd-e-sn-datasheet.pdf). Every pin and spec above cites its page.
• Footprint: provenance/footprint-check.json, pad by pad against p.25 and against KiCad's footprint.
• 3D model: provenance/3d-model.json: source attempts, the KiCad comparison with method and numbers, build parameters, etch gate, hashes. The tools are in provenance/tools/; KiCad's reference footprint and model are kept in provenance/kicad-reference/ for the comparison.
• Symbol: created from provenance/tools/symbol-create.json by adom-symbol 1.2.6, then every pin moved onto the 2.54 mm grid by snap_symbol.py (the tool placed the first pin of each column at y = -2.00 mm).
• Licence: Adom-authored files (symbol, footprint, models, etch, artwork, libraries, tools, text) are CC-BY-4.0, see LICENSE. The datasheet is Microchip's and keeps Microchip's terms; the KiCad reference files keep CC-BY-SA 4.0 with the KiCad libraries exception.

Cited datasheet pages: