board

OCuLink Riser for the Supermicro AIOM Slot

Public Unreviewed

by John Lauer

Passive OCP NIC 3.0 SFF card that breaks a Supermicro AIOM slot's PCIe x16 into four OCuLink 4i ports (4 x4, Gen4): 6-layer, 85 ohm, length-matched, DRC-clean KiCad project with Gerbers, BOM and CPL.

pcbkicadoculinksff-8611ocp-nic-3.0aiomsupermicropcie-gen4riseropen-hardware
Overview Files Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
oculink-aiom-riser / README.md
History Download
John Lauer Lead with the video, then the 3D render and the 3D tour; board GLB from adom-aiflow 0.1.92 board-glb copper (ENIG pads, opaque silkscreen) 9d37b14 7d ago

OCuLink Riser for the Supermicro AIOM Slot

Download the video · captions: VTT, SRT

The riser in 3D: gold fingers at the front, four OCuLink receptacles on the faceplate edge

A passive card for Supermicro's AIOM slot (OCP NIC 3.0 small form factor) that breaks the PCIe x16 link out to four OCuLink (SFF-8611) ports, so NVMe drives or a GPU can be cabled out at PCIe Gen4. It was built for a YouTube viewer who asked for one, by Claude in Adom Hydrogen with adom-aiflow and KiCad.

Status: designed and checked, not yet built. The KiCad project, Gerbers, drill files, BOM and pick-and-place are all here. Nobody has fabricated or tested a card yet. If you build one, please open an issue on this page with what you found.

3D tour: the card and its new component pages

A walk around the finished card in Adom's 3D viewer: the four OCuLink receptacles, the ESD arrays, the reset buffer and power-good supervisor, the OCP scan chain and FRU EEPROM, the gold fingers and the underside. Then the two component pages this build added to the wiki: the Amphenol G14A42111C12HR OCuLink receptacle and the ROHM BR24H64FJ-5ACE2 EEPROM. Download the tour · captions: VTT, SRT.

What it does
Plugs into Supermicro AIOM / OCP NIC 3.0 SFF slot (4C+ edge, 168 pins)
Gives you 4 x OCuLink 4i ports, each a PCIe x4 link with its own REFCLK and PERST#
Speed PCIe Gen4 (16 GT/s per lane)
Active parts in the signal path none: no switch, no retimer, no redriver
Board 76 x 115 mm, 6 layers, 85 ohm controlled impedance, hard gold fingers

Before you plug it in

  1. Set the slot to x4x4x4x4 in the BIOS. The card tells the host it is a "4 x4" card (OCP present pins 0b0011), but most Supermicro BIOSes still need the AIOM slot's bifurcation set by hand. Without it the host trains one x16 link, and you see port 0 or nothing.
  2. Use short Gen4 cables. OCuLink at Gen4 has little margin to spare: 0.5 m or shorter SFF-8611 cables rated for Gen4. At the device end you need an OCuLink-to-U.2/M.2/PCIe adapter, a device-side card (the cable carries the host's REFCLK and PERST#).
  3. Make a faceplate. The card has the SFF outline and the faceplate grounding holes, but a stock SFF blank has no openings for four OCuLink receptacles. Cut one, or print a bracket.
  4. Program the FRU (optional). Some BMCs read the card's FRU EEPROM to identify it. Bridge JP1, write design/fru.bin, open JP1 again. Details in the design record.

Order it

  • PCB: send fab/gerbers.zip to JLCPCB: 6 layers, 1.6 mm, impedance control with stackup JLC06161H-3313, ENIG, gold fingers with 30 degree bevel, via-in-pad (filled and capped). The trace widths for 85 ohm on that stackup are in the design record.
  • Parts: fab/bom.csv (Mouser part numbers, stock checked 2026-10-12) and fab/cpl.csv for assembly; all parts sit on the top side. The TPS3808 supervisor had low stock (89 at Mouser), so order it early.

Components

Every part links to its Adom component page (symbol, footprint, 3D model, provenance).

Part Qty Refs Value Role Buy
CL05B104KO5NNNC
CL05B104KO5NNNC
Samsung Electro-Mechanics		 4 C1, C2, C3, C4 100n decoupling Mouser 187-CL05B104KO5NNNC
CL10A106KQ8NNNC
CL10A106KQ8NNNC
Samsung Electro-Mechanics		 1 C5 10u 3.3 V aux bulk Mouser 187-CL10A106KQ8NNNC
IN-S63BTG
IN-S63BTG
Inolux		 2 D1, D2 GREEN 3.3 V aux / 12 V present LEDs Mouser 743-IN-S63BTG
G14A42111C12HR
G14A42111C12HR
Amphenol Commercial Products		 4 J2, J3, J4, J5 G14A42111C12HR OCuLink 4X receptacle, one per x4 port Mouser 523-G14A42111C12HR
RC0402FR-07100RL
RC0402FR-07100RL
YAGEO		 2 R1, R2 100 present-pin straps (PRSNTB2#/3#) Mouser 603-RC0402FR-07100RL
RC0402FR-071KL
RC0402FR-071KL
YAGEO		 3 R3, R6, R23 1k scan-chain pull-ups, LED Mouser 603-RC0402FR-071KL
RC0402FR-0710KL
RC0402FR-0710KL
YAGEO		 4 R4, R5, R8, R9 10k pull-ups/downs Mouser 603-RC0402FR-0710KL
RC0402FR-07100KL
RC0402FR-07100KL
YAGEO		 5 R7, R15, R16, R17, R18 100k PERST# pull-downs, supervisor Mouser 603-RC0402FR-07100KL
RC0402FR-0733RL
RC0402FR-0733RL
YAGEO		 4 R11, R12, R13, R14 33 PERST# series resistors Mouser 603-RC0402FR-0733RL
RC0402FR-074K7L
RC0402FR-074K7L
YAGEO		 1 R24 4.7k 12 V LED resistor Mouser 603-RC0402FR-074K7L
SN74LV165APWRE4
SN74LV165APWRE4
Texas Instruments		 1 U1 SN74LV165APWR OCP scan chain (present and status bits) Mouser 595-SN74LV165APWRE4
BR24H64FJ-5ACE2
BR24H64FJ-5ACE2
ROHM Semiconductor		 1 U2 BR24H64FJ-5ACE2 FRU EEPROM on the slot SMBus Mouser 755-BR24H64FJ-5ACE2
TPS3808G33DBVTG4
TPS3808G33DBVTG4
Texas Instruments		 1 U3 TPS3808G33 NIC_PWR_GOOD supervisor Mouser 595-TPS3808G33DBVTG4
SN74LVC125APWR
SN74LVC125APWR
Texas Instruments		 1 U4 SN74LVC125APWR buffers each port's PERST# Mouser 595-SN74LVC125APWR
TPD4E05U06QDQARQ1
TPD4E05U06QDQARQ1
Texas Instruments		 4 U5, U6, U7, U8 TPD4E05U06 ESD on each port's sideband Mouser 595-PD4E05U06QDQARQ1

No-part features (the gold-finger edge J1, faceplate holes H1/H2, test pads TP1-TP12, solder jumper JP1) are copper on the board.

How it was designed

The full engineering record is in design/README.md: the spec sources, the pinout and present-pin straps, the stackup and the field-solver widths, the lane-reversal routing, skew per port, and the checks. In short:

  • 85 ohm pairs on three signal layers, between solid ground planes.
  • Every pair matched within 0.017 mm, every port's four lanes matched to 0.01 ps.
  • One REFCLK and one buffered PERST# per port.
  • KiCad DRC with JLCPCB's 6-layer rules: 0 errors, 0 unconnected (4 cosmetic library-match warnings, explained in the design record).
  • Current and heat solved on all six layers: 47 A/mm² peak against a 60 A/mm² limit; the card warms by less than 0.1 °C.

Top: every part labelled, test points named, finger groups numbered Bottom: board identity, BIOS note, A-side finger numbers

File What
kicad/ the KiCad 10 project: board, schematic, project library, 3D models, design rules
fab/ gerbers.zip (Gerbers + Excellon drill), bom.csv, cpl.csv, and export-check.json (every file re-read against the board)
design/ the design record, calculations, test plan and FRU image
gen/ the generator scripts
docs/ renders, the current/heat figures, part icons, and the aiflow run record (docs/runs/)

Open source

Everything that made this board is in this page's Files tab: the KiCad 10 project in kicad/, and the Python that generated it in gen/ (netlist, footprints from the OCP and Amphenol drawings, outline, placement, the high-speed router with lane reversal and delay matching, the maze router for the slow nets, silkscreen, export).

  1. Get it: adom-wiki repo clone john/oculink-aiom-riser, then open kicad/ocp-oculink-riser.kicad_pro in KiCad 10.
  2. Rebuild it: gen/run_pipeline.sh regenerates the schematic, board and checks from gen/design.py; gen/export_fab.py writes and re-checks the Gerbers, BOM and CPL. The scripts call KiCad 10's kicad-cli and python.exe from a Windows install (paths at the top of each script); the container-side ones need shapely, scipy and numpy.
  3. Change it with an AI: open the folder in Claude Code and describe what you want, for example "route port 3 to a vertical OCuLink receptacle", "add a REFCLK buffer", or "make a 2-port 4C version".
  4. Send it back: open a pull request on this page, or start a discussion with what you built and what you measured.

License

Open hardware: the board files, the design record and the scripts are CC-BY-4.0. Build it, change it, sell it; credit this page.

Build clips: watch it being made

Build clips
    Build clips    		 Every part of the build, filmed off the screen and cut to 16x speed with a voice-over explaining what is happening. The build clips run from the viewer's request through the spec research, the impedance math, routing and the board in KiCad. Watch them in order to see how an AI engineers a high-speed PCB end to end.

Watch the clips