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SN74LV165APWR
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LV165APWR
Texas Instruments · Shift Registers · TSSOP-16
SN74LV165APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SH/LD | input | Load/Shift control input; low selects parallel load mode, high selects serial shift mode. |
| 2 | CLK | input | Storage clock input; low-to-high transition shifts data when SH/LD is high and CLK INH is low. |
| 3 | E | input | Serial input E; parallel input loaded to register stage E when SH/LD is low. |
| 4 | F | input | Serial input F; parallel input loaded to register stage F when SH/LD is low. |
| 5 | G | input | Serial input G; parallel input loaded to register stage G when SH/LD is low. |
| 6 | H | input | Serial input H; parallel input loaded to register stage H when SH/LD is low. |
| 7 | Q H | output | Output H, inverted; complementary serial output from register stage H. |
| 8 | GND | power_in | Ground pin; 0 V reference. |
| 9 | QH | output | Output H; serial output from register stage H. |
| 10 | SER | input | Serial input; input data shifted into first register stage on clock transitions. |
| 11 | A | input | Serial input A; parallel input loaded to register stage A when SH/LD is low. |
| 12 | B | input | Serial input B; parallel input loaded to register stage B when SH/LD is low. |
| 13 | C | input | Serial input C; parallel input loaded to register stage C when SH/LD is low. |
| 14 | D | input | Serial input D; parallel input loaded to register stage D when SH/LD is low. |
| 15 | CLK INH | input | Clock inhibit input; must be low during CLK-based shifts or triggers shift via low-to-high transition when CLK is high. |
| 16 | VCC | power_in | Power pin; positive supply voltage 2 V to 5.5 V per operating specifications. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74LV165APWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74lv165apwr-etched.step/sn74lv165apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv165apwr.step/sn74lv165apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
9713235082974c29, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).