OCuLink Riser for the Supermicro AIOM Slot - video/oculink-riser.vtt

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John Lauer Videos: sentence-exact captions (VTT+SRT), no dead air; new 3D tour of the card and its component pages 045ee35 7d ago

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WEBVTT

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A YouTube viewer asked for an OCuLink
riser for the AIOM slot on their
Supermicro server.

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Before we build it, here is what that
means.

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This is the kind of server the viewer has:
a Supermicro rack server.

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Inside, besides the normal PCIe slots,

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newer Supermicro boards have one or two
AIOM slots.

00:00:20.367 --> 00:00:27.982
From the back, Supermicro labels them:
PCIe x16, AIOM, OCP 3.0.

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A full sixteen lane slot, the same
bandwidth as a graphics card slot.

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But only one kind of card fits: an AIOM
network card like this one.

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If you don't need another network card,
those sixteen lanes sit unused.

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This board changes that.

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It plugs into the AIOM slot in place of
the network card,

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and splits the sixteen lanes into four
OCuLink ports, each a full PCIe x4 link.

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Run an OCuLink cable from each port to a
U.2 NVMe drive,

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and the server gains four more fast
drives, each running at full Gen 4x4
speed,

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about eight gigabytes per second.

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Or cable a port to an OCuLink dock like
this one,

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and hang a graphics card or another PCIe
card off the server, outside the case.

00:01:13.300 --> 00:01:17.992
There is one catch: the server's BIOS has
to support splitting that slot four ways.

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When it does, an unused network slot
becomes four general purpose PCIe ports.

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Now the build.

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We typed that one request into Claude, in
Adom Hydrogen.

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It reads the OCP 3.0 spec and the OCuLink
standards, pinout tables and all.

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It writes a small field solver and finds
trace widths for 85 ohm differential pairs
on a six layer stack-up.

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Thirty six high speed pairs are routed
from the gold fingers to four OCuLink
connectors,

00:01:45.475 --> 00:01:46.513
with no crossings.

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Every lane in a port is tuned to arrive
within a hundredth of a picosecond of its
neighbors.

00:01:51.1000 --> 00:01:54.350
The design record: impedance per layer,

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skew inside every pair under two
hundredths of a millimeter.

00:01:58.200 --> 00:02:03.295
On the adom-aiflow timeline, the run moves
through design rules:

00:02:03.295 --> 00:02:05.444
JLCPCB's six layer process.

00:02:05.700 --> 00:02:09.690
Then the real board opens in KiCad: gold
fingers at the bottom,

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connectors at the top.

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Forty seven parts land live, one at a
time, each its own undo step.

00:02:16.467 --> 00:02:19.469
Then one hundred sixty nine traces land
the same way,

00:02:19.469 --> 00:02:21.904
every one checked against the design
rules.

00:02:22.167 --> 00:02:24.366
The current check needs a real field
solve.

00:02:24.486 --> 00:02:26.036
Claude finds why it fails:

00:02:26.036 --> 00:02:29.495
a tenth of a millimeter via ring the
solver could not see.

00:02:29.733 --> 00:02:32.813
With a finer grid, current and thermal
both pass.

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Clean silkscreen, and the finished board
in KiCad's 3D viewer:

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every test point and port labeled.

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Gerbers for all six copper layers, drill
files,

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pick and place and the bill of materials,

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each read back and checked against the
board.

00:02:47.667 --> 00:02:51.766
Finish passes: zero design rule errors,
zero unconnected.

00:02:51.886 --> 00:02:56.297
A manufacturable PCI Express Gen4 card,
from a one line comment,

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designed and checked by Claude in Adom
Hydrogen.