# Control-Panel Workcell V2.0.1 — Board Capabilities

**A Raspberry Pi Compute Module 5 carrier and smart power-distribution hub for Adom workcells.**
It takes four bench/PSU inputs, meters every rail with 20-bit precision, switches power and
debug out to a docked Scaffold board (RP2350 + user breakouts), and provides the workcell's
network, USB, CAN-FD, wireless, sensing, and indicator infrastructure.

| | |
|---|---|
| Project | `control-panel_workcell` rev **V2.0.1** (KiCad, 7 hierarchical sheets) |
| Compute | Raspberry Pi **CM5** (CM5 Lite assumed — microSD boot, nRPIBOOT not broken out) |
| Board | 172 × 72 mm, **6-layer** (F / In1–In4 / B) |
| Status | DRC clean — 0 violations, 0 unconnected pads (report 2026-06-10) |
| Open hardware | OSHW logo on root sheet |

---

## 1. Power input & distribution

Four independent supply inputs land on **J1** (WAGO 2604-1108, 8-position, dual contacts
per pole) and are individually metered. Three of them are delivered to the docked Scaffold
board through **J2** (Samtec ET60S-S03 — three 60 A-class power blades + 25 signal pins).

### Rail plan (root-sheet table, IPC-2152 minimums @20 °C)

| Rail | Voltage | Current | Function | Path |
|------|---------|---------|----------|------|
| **PS1** | 0–60 V | 12 A (controlled) | USER — variable rail to Scaffold | J1 → 13 mΩ shunt → J2 blade P1 |
| **PS2** | 5 V | 10 A (relayed) | USER — switched rail to Scaffold | J1 → 16 mΩ shunt → TPS22990 load switch → J2 blade P2 |
| **PS3** | spare (rated 24 V) | spare | USER — future rail | J1 → (shunt unpopulated) → J2 blade P3 |
| **PS4** | 5 V | 10 A (7 A realistic) | CONTROL — powers this board + CM5 | J1 → 6.3 A fuse (Littelfuse Nano2 045106.3MRL) → 16 mΩ shunt → CM5 / regulators |
| +3v3 | 3.3 V | 3 A | Board logic | AP3441 buck (U5) from PS4, enabled by CM5 `VBUS_EN` (pin 111) |
| M.2 3.3 V | 3.3 V | 3 A max | M.2 Key-E slot | AP3441 buck (U14) from PS4, enabled by CM5 `PCIE_PWR_EN` (pin 106) |

**PS2 switching ("relay"):** CM5 `CAM_GPIO1` (pin 100) → NSi8210 digital isolator (U6) →
TPS22990 10 A load switch (3.9 mΩ R<sub>ON</sub>, controlled 3 ms slew). The isolator lets PS2's
return (`-PS2`) float up to 2.5 V from common ground. Readback channel senses the switched state.

**Grounding:** machine-pin jumpers select the scheme — jumper installed: common GND is
bonded to EGND; uninstalled: supply grounds float. PS1/PS2/PS3 returns are carried as
separate nets to the J2 blades.

**Protection:** PS4 — 6.3 A fuse + SMBJ6.0A TVS (D1) + PTVS7V5 on the protected node.
USB VBUS — TPS25940 eFuse (see §4).

### Power telemetry — 4× INA228 (20-bit, ±0.05 %)

All four on CM5 **I2C1** (`PWR_I2C-1`, GPIO2/3), alert pins unused; Kelvin-sensed
2512 3 W 1 % shunts with 0 Ω sense links and RC filtering:

| Device | Rail | Address | Shunt | Range / resolution |
|--------|------|---------|-------|--------------------|
| U2 | PS1 | `0x45` | 13 mΩ | 0–12.6 A, floor 24 µA, 1.87 W @12 A |
| U3 | PS2 | `0x44` | 16 mΩ | 0–10.24 A, floor 19.5 µA, 1.6 W @10 A |
| U4 | PS3 | `0x41` | (fit with PS3) | bus-voltage monitoring ready |
| U1 | PS4 | `0x40` | 16 mΩ | 0–10.24 A |

Each INA228 also reads its rail's bus voltage (0–85 V capable — covers PS1's 60 V range).

---

## 2. Compute — CM5 socket

- Two Hirose-style 100-pin connectors (**J4** = pins 1–100, **J7** = pins 101–200).
  Full pin map: see *CM5_Pinout_Tree.md*.
- **microSD** (Molex 503398-1892, J5) on the SDIO bus — SDR25 @50 MHz. SD power gated by an
  RT9742 current-limited switch (`SD_PWR_ON`). *SD signals only exist on CM5 Lite (no eMMC);
  nRPIBOOT is not broken out, so plan on Lite modules + SD imaging.*
- Power button (SW1), buffered power LED (Q1), activity LED, EEPROM write-protect jumper (JP5).
- No RTC backup battery (VBAT n.c.); HDMI, MIPI CSI/DSI, and fan header are unused — headless box.
- CM5 5 V input budget: CPU peak ~2.5 A, GPU unused (designer note).

---

## 3. Networking

| Interface | Implementation |
|-----------|----------------|
| **Gigabit Ethernet** | CM5 PHY direct to HR911130A integrated-magnetics RJ45 (J6) with green/yellow speed LEDs + activity LED. Length-tuned (400 ps rule, critical length ≈33 mm). |
| **Wi-Fi (PCIe)** | M.2 **Key-E** slot (J8): PCIe Gen2 x1 (90 Ω matched), CLKREQ/WAKE/PERST, dedicated 3.3 V buck, M2×1.5 standoff. Intended module: Intel **AX210**-class. |
| **Bluetooth (USB)** | AX210 BT runs over USB2: CM5 USB3-1 D± is routed through a TMUXHS221 2:1 mux — **NC = Bluetooth, NO = USB-A connector**. GPIO27 selects, GPIO17 enables. *USB-A USB2 and Bluetooth are mutually exclusive.* |
| **CAN FD** | MCP251863 (U15 — MCP2518FD controller + ATA6563 transceiver, 40 MHz crystal) on CM5 **SPI4** (GPIO5–11, three interrupt lines). CANH/L exit on J3 (WAGO 2060-452, dual contacts per pole for daisy-chaining) with split-termination jumper **JP6** (open = unterminated). |

---

## 4. USB

| Port | Lanes | Power | Notes |
|------|-------|-------|-------|
| **USB-C (J10)** | CM5 **USB3-0** SS pair via HD3SS3212 orientation mux + D± | Source: PS2 → TPS25940 eFuse (I<sub>LIM</sub> 4.45 A, OVP 5.68 V, UVLO 4.29 V) → Q2 P-FET | TUSB321 CC controller strapped **DFP (host), 3.0 A advertised**; CM5 `USB_OTG` strapped host. ESD on all pairs. |
| **USB-A 3.0 (J9)** | CM5 **USB3-1** SS pair direct; D± via TMUXHS221 (shared with Bluetooth) | VBUS from the same TPS25940 output | Full SuperSpeed regardless of mux; USB2 only when mux is set to NO |
| **USB 2.0 (internal)** | CM5 dedicated USB2 port (pins 103/105) | — | Hard-wired to the on-board **PiProbe** debug molecule |

---

## 5. Scaffold dock (J2 — Samtec ET60S-S03)

The board's purpose: dock a **Scaffold board** carrying an RP2350 and user breakouts.

- **Power blades:** P1 = PS1 (0–60 V metered), P2 = PS2 (5 V, CM5-switched), P3 = PS3 (spare).
  Five contacts per blade polarity, separate returns.
- **Debug:** SWD (`DEBUG_SWD`/`DEBUG_SWCLK`) and UART (`DEBUG_TX`/`DEBUG_RX`) from the
  on-board PiProbe — the CM5 can flash/debug the Scaffold RP2350 with stock `openocd`/`picotool`
  tooling. `MCU_BOOT` (CAM_GPIO0) and `MCU_RST` (GPIO21) give the CM5 direct boot-strap/reset
  control of the RP2350.
- **Spare GPIO:** 4 lines (GPIO0/4/14/15) to J2 via jumpers JP1–JP4 — GPIO14/15 can instead be
  the Linux serial console (`enable_uart=1`).
- **Rails out:** +3v3 and +PS4 (5 V) service pins, plus grounds.

---

## 6. Embedded molecules (Adom standard slots)

| Slot | Molecule | Bus | Function |
|------|----------|-----|----------|
| N1 | **PiProbe v1.2** (RP2040, footprint-identical to the Raspberry Pi Debug Probe) | CM5 USB2 | CMSIS-DAP SWD + UART bridge to the Scaffold RP2350; its own BOOTSEL/RST are CM5-controlled (GPIO22/23) so the CM5 can re-flash the probe itself |
| N2, N4 | **8×8 mm Bosch-standard sensor slots** (swappable — e.g. BME690 gas/T/H/P, BMA accelerometer) | `SENSOR_I2C-2` (GPIO12/13) + shared INT (GPIO16) | Environmental / motion sensing; any 8×8 molecule with the standard VCC/SCL/GND/SDA/INT1/INT2 pad ring fits |
| N3 | **I2S MEMS microphone carrier** (mono, SEL = GND) | `MIC_I2S-0` (GPIO18/19/20) | Audio capture |

---

## 7. Indicators

- **TCA6424A** 24-bit I2C expander (U16, addr `0x22`, on I2C0 / `LED_I2C-0`, reset from ID_SC).
- Drives **18 blue LEDs arranged in a ring** (placement angles −155°…170° — designer note:
  *"pulse LEDs in cycle to view camera functionality"*) plus 4 status LEDs
  (2 red, 2 green: power/system states). 6 expander ports spare.
- RJ45 bezel LEDs driven directly by the CM5 Ethernet LED pins.

---

## 8. I2C / bus map (CM5 side)

| Bus | CM5 pins | Devices |
|-----|----------|---------|
| I2C0 (`LED_I2C-0`) | SCL0/SDA0 (80/82) | TCA6424A @0x22, CM5 ID EEPROM domain |
| I2C1 (`PWR_I2C-1`) | GPIO2/3 (56/58, internal 1.8 k pulls) | INA228 ×4 @0x40/0x41/0x44/0x45 |
| I2C (`SENSOR_I2C-2`) | GPIO12/13 + INT GPIO16 | Sensor molecule slots N2/N4 |
| SPI4 (`CAN_SPI-4`) | GPIO5–11 | MCP251863 CAN-FD |
| I2S0 (`MIC_I2S-0`) | GPIO18/19/20 | MEMS mic slot N3 |
| USB2 | 103/105 | PiProbe |
| Free GPIO | GPIO26 only (pin 24) | — |

---

## 9. Review notes (V2.0.1)

1. **Ethernet pair 2 polarity** — pin 9 (`Pair2_N`) → `TRD2_P`, pin 11 (`Pair2_P`) → `TRD2_N`.
   Benign in practice (GbE PHYs auto-correct per-pair polarity), but worth normalizing.
2. **`Input Power.kicad_sch` is orphaned** — present in the project folder but no longer in the
   sheet hierarchy (superseded by `Input_Sense`). Its INA228 address notes ("+5V_CAN",
   "+5V_DED", "VARIABLE") survive as stale text. Consider deleting to avoid confusion.
3. **No RTC battery / no nRPIBOOT** — fine for CM5 Lite + SD workflow, but eMMC modules can't
   be provisioned in-system and the RTC won't keep time across power loss.
4. **PS3 shunt deliberately unpopulated** — schematic note: "Add PS3 shunt when supply is
   populated." Document in the build/BOM notes so telemetry isn't silently dead on PS3.
5. DRC: clean (NPTH-in-courtyard, footprint-type and library-mismatch checks ignored by config).

---

*Companion documents: `CM5_Pinout_Tree.md` (full 200-pin tree + tables),
`cm5_pinout_tree.html` (interactive), `Control-Panel_Workcell_V2.0.1_Spec.pdf` (shareable spec).*