component
XL7026E1
Public Made by Adomby adom
XLSEMI DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
John Lauer
Regenerate .lbr with adom-lbr 2.31.0. Since the 2.24.0 pass these pages gained: rounded and oval pad corners that were importing square (EAGLE roundness), pin names hidden on glyph symbols so they stop printing over the drawing, group captions using EAGLE's real alignment vocabulary, >NAME and >VALUE kept out of the pin/wire lanes, and KiCad user-layer geometry preserved. Verified with lint and validate.
d84bf3a
1mo ago
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<!DOCTYPE eagle SYSTEM "eagle.dtd">
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<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
</layers>
<library>
<description>XLSEMI DC-DC Converters, SOP-8-EP</description>
<packages>
<package name="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm">
<description>SOIC-8-1EP, 3.9 x 4.9 mm, 1.27 mm pitch</description>
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<wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>
<text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">>NAME</text>
<text x="0" y="-3.480" size="1.27" layer="27" align="top-center">>VALUE</text>
</package>
</packages>
<symbols>
<symbol name="XL7026E1">
<description>XLSEMI DC-DC Converters, SOP-8-EP</description>
<wire x1="-12.7" y1="7.62" x2="12.7" y2="7.62" width="0.254" layer="94"/>
<wire x1="12.7" y1="7.62" x2="12.7" y2="-7.62" width="0.254" layer="94"/>
<wire x1="12.7" y1="-7.62" x2="-12.7" y2="-7.62" width="0.254" layer="94"/>
<wire x1="-12.7" y1="-7.62" x2="-12.7" y2="7.62" width="0.254" layer="94"/>
<text x="0.0000" y="10.1600" size="1.27" layer="95" align="center">>NAME</text>
<text x="0.0000" y="-10.1600" size="1.27" layer="96" align="center">>VALUE</text>
<pin name="FB" x="-17.78" y="5.08" length="middle" direction="in"/>
<pin name="VREG" x="-17.78" y="2.54" length="middle" direction="pwr"/>
<pin name="VC" x="-17.78" y="0" length="middle" direction="pas"/>
<pin name="VIN" x="-17.78" y="-2.54" length="middle" direction="pwr"/>
<pin name="SW" x="-17.78" y="-5.08" length="middle" direction="out"/>
<pin name="EP" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>
<pin name="GND" x="17.78" y="0" length="middle" direction="pwr" rot="R180"/>
<pin name="OGND" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>
<pin name="SW@2" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="XL7026E1" prefix="U">
<description>XLSEMI DC-DC Converters, SOP-8-EP</description>
<gates>
<gate name="G$1" symbol="XL7026E1" x="0" y="0"/>
</gates>
<devices>
<device name="" package="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm">
<connects>
<connect gate="G$1" pin="FB" pad="1"/>
<connect gate="G$1" pin="VREG" pad="2"/>
<connect gate="G$1" pin="VC" pad="3"/>
<connect gate="G$1" pin="VIN" pad="4"/>
<connect gate="G$1" pin="SW" pad="5"/>
<connect gate="G$1" pin="EP" pad="9"/>
<connect gate="G$1" pin="GND" pad="8"/>
<connect gate="G$1" pin="OGND" pad="7"/>
<connect gate="G$1" pin="SW@2" pad="6"/>
</connects>
<technologies>
<technology name="">
<attribute name="MPN" value="XL7026E1" constant="no"/>
<attribute name="MANUFACTURER" value="XLSEMI" constant="no"/>
<attribute name="LCSC_PN" value="C89529" constant="no"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>