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XL7026E1

Public Made by Adom

by adom

XLSEMI DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs xl7026e1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
pads.json footprint: the shipped SOIC-8 has no thermal pad, but the symbol and the datasheet both show 9 pads. datasheet EP 2.29x3.1mm, nearest land 2.29x3.0mm (delta 0.10mm). Chosen from this part's OWN datasheet, not inferred from a sibling - the Richtek SOP-8-EP parts alone carry three different exposed-pad sizes, so family inference would have been wrong. Rebuilds the .lbr, re-derives pin 1 and pads.json. · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 10d ago
README.md xl7026e1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
xl7026e1-etched.fit.json xl7026e1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
xl7026e1-etched.glb xl7026e1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
xl7026e1-etched.step xl7026e1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
xl7026e1.glb 3D: replace the model to match the corrected SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm footprint. The page shipped the plain SOIC-8 body, not the exposed-pad land, which no longer depicted the part after the footprint was fixed from its datasheet. Model is the exact one the new footprint references in the KiCad official library (CC-BY-SA 4.0), the same provenance page.json already records; .glb regenerated from it via service-step2glb. · Ray 1mo ago
xl7026e1.kicad_mod footprint: the shipped SOIC-8 has no thermal pad, but the symbol and the datasheet both show 9 pads. datasheet EP 2.29x3.1mm, nearest land 2.29x3.0mm (delta 0.10mm). Chosen from this part's OWN datasheet, not inferred from a sibling - the Richtek SOP-8-EP parts alone carry three different exposed-pad sizes, so family inference would have been wrong. Rebuilds the .lbr, re-derives pin 1 and pads.json. · Ray 1mo ago
xl7026e1.kicad_sym Publish 0.1.0 · Ray 1mo ago
xl7026e1.lbr Regenerate .lbr with adom-lbr 2.31.0. Since the 2.24.0 pass these pages gained: rounded and oval pad corners that were importing square (EAGLE roundness), pin names hidden on glyph symbols so they stop printing over the drawing, group captions using EAGLE's real alignment vocabulary, >NAME and >VALUE kept out of the pin/wire lanes, and KiCad user-layer geometry preserved. Verified with lint and validate. · John Lauer 1mo ago
xl7026e1.step 3D: replace the model to match the corrected SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm footprint. The page shipped the plain SOIC-8 body, not the exposed-pad land, which no longer depicted the part after the footprint was fixed from its datasheet. Model is the exact one the new footprint references in the KiCad official library (CC-BY-SA 4.0), the same provenance page.json already records; .glb regenerated from it via service-step2glb. · Ray 1mo ago

XL7026E1

XLSEMI · DC-DC Converters · SOP-8-EP

XL7026E1 from XLSEMI, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB input Feedback pin. Sensed against the internal 1.25 V reference through an external resistor divider from VOUT to set the output voltage (VOUT = 1.25 * (1 + R2/R1)).
2 VREG power_in Chip supply pin. Requires a 10 µF decoupling capacitor between VREG and GND to filter noise. An external 7-9 V bias can be applied to this pin to reduce internal power dissipation.
3 VC passive Internal voltage-regulator bypass pin. Requires a 1 µF ceramic capacitor connected between VC and VIN.
4 VIN power_in Main power input, DC 12-90 V (demo tested up to 84 V). Bypass to GND with an electrolytic capacitor placed close to the pin to suppress switching noise and inrush spikes.
5 SW power_out Power-switch output pin. Connects to the external inductor and freewheeling Schottky diode of the buck converter. Tied together with pin 6 for current handling.
6 SW power_out Power-switch output pin (paralleled with pin 5). Connects to the switching node of the buck converter.
7 OGND power_in Power/output ground return for the internal power stage. Tie to the ground plane at the input capacitor return.
8 GND power_in Signal ground reference for the control circuitry.
9 EP power_in Exposed thermal pad on the bottom of the SOP8-EP package. Solder to the ground copper pour for heat sinking; connect to GND.

Key specifications

Parameter Value
Manufacturer XLSEMI
Package SOP-8-EP
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • XL7026E1

CAD (KiCad official)

  • Symbol: XL7026E1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-EP (KiCad packages3D, STEP)
  • 3D model files: xl7026e1-etched.step / xl7026e1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl7026e1.step / xl7026e1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XLSEMI datasheet (8 pp, sha256 56a8aedb64fd6229, retrieved 2026-08-17, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF