# WSP6956

**Winsok Semicon** · MOSFETs · SOP-8

WSP6956 from Winsok Semicon, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1 (N-channel). |
| 2 | G1 | input | Gate of MOSFET 1, VGS rated ±20V maximum. |
| 3 | S2 | passive | Source of MOSFET 2 (N-channel). |
| 4 | G2 | input | Gate of MOSFET 2, VGS rated ±20V maximum. |
| 5 | D2 | passive | Drain of MOSFET 2, VDSS 60V, 10A continuous at TA=25°C. |
| 6 | D2 | passive | Drain of MOSFET 2, VDSS 60V, 10A continuous at TA=25°C. |
| 7 | D1 | passive | Drain of MOSFET 1, VDSS 60V, 10A continuous at TA=25°C. |
| 8 | D1 | passive | Drain of MOSFET 1, VDSS 60V, 10A continuous at TA=25°C. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Winsok Semicon |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDSS |  |  | 60 | V |  | 1 |
| Gate-Source Voltage | VGSS | -20 |  | 20 | V |  | 1 |
| Maximum Junction Temperature | TJ |  |  | 150 | °C |  | 1 |
| Storage Temperature Range | TSTG | -55 |  | 150 | °C |  | 1 |
| Diode Continuous Forward Current | IS |  |  | 5 | A | TA=25°C | 1 |
| Continuous Drain Current | ID |  |  | 10 | A | TA=25°C | 1 |
| Continuous Drain Current | ID |  |  | 8 | A | TA=70°C | 1 |
| Pulsed Drain Current | IDM |  |  | 38 | A | TA=25°C | 1 |
| Maximum Power Dissipation | PD |  |  | 3.5 | W | TA=25°C | 1 |
| Maximum Power Dissipation | PD |  |  | 2.2 | W | TA=70°C | 1 |
| Avalanche Current, Single pulse | IAS |  |  | 27 | A | L=0.1mH | 1 |
| Avalanche Energy, Single pulse | EAS |  |  | 36 | mJ | L=0.1mH | 1 |
| Thermal Resistance Junction to Ambient | RθJA |  |  | 35 | °C/W | t 10s | 1 |
| Thermal Resistance Junction to Ambient | RθJA |  |  | 70 | °C/W | Steady state | 1 |
| Drain-Source Breakdown Voltage | BVDSS | 60 |  |  | V | VGS=0V, IDS=250µA | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 1 | µA | VDS=48V, VGS=0V | 2 |
| Zero Gate Voltage Drain Current | IDSS |  |  | 30 | µA | TJ=85°C | 2 |
| Gate Threshold Voltage | VGS(th) |  |  | 2.5 | V | VDS=VGS, IDS=250µA | 2 |
| Gate Leakage Current | IGSS | -100 |  | 100 | nA | VGS=±20V, VDS=0V | 2 |
| Drain-Source On-state Resistance | RDS(ON) |  | 15 | 20 | mΩ | VGS=10V, IDS=10A | 2 |
| Drain-Source On-state Resistance | RDS(ON) |  | 18 | 24 | mΩ | VGS=4.5V, IDS=9A | 2 |
| Diode Forward Voltage | VSD |  | 0.8 | 1.3 | V | ISD=10A, VGS=0V | 2 |
| Input Capacitance | Ciss |  | 1370 | 1780 | pF | VGS=0V, VDS=30V, Frequency=1.0MHz | 2 |
| Turn-on Delay Time | td(ON) |  | 14 | 26 | ns | VDD=30V, RL=30Ω, IDS=1A, VGEN=10V, RG=6Ω | 2 |
| Turn-on Rise Time | tr |  | 8 | 15 | ns | VDD=30V, RL=30Ω, IDS=1A, VGEN=10V, RG=6Ω | 2 |
| Turn-off Delay Time | td(OFF) |  | 38 | 69 | ns | VDD=30V, RL=30Ω, IDS=1A, VGEN=10V, RG=6Ω | 2 |
| Turn-off Fall Time | tf |  | 12 | 22 | ns | VDD=30V, RL=30Ω, IDS=1A, VGEN=10V, RG=6Ω | 2 |
| Total Gate Charge | Qg |  | 26 | 37 | nC | VDS=30V, VGS=10V, IDS=10A | 2 |
| Total Gate Charge | Qg |  | 12 |  | nC | VDS=30V, VGS=4.5V, IDS=10A | 2 |
| Reverse Recovery Time | trr |  | 21 |  | ns | ISD=10A, dISD/dt=100A/µs | 2 |
| Reverse Recovery Charge | Qrr |  | 22 |  | nC |  | 2 |
| Gate Resistance | RG |  | 2.5 |  | Ω | VGS=0V, VDS=0V, f=1MHz | 2 |
| Output Capacitance | Coss |  | 135 |  | pF |  | 2 |
| Reverse Transfer Capacitance | Crss |  | 60 |  | pF |  | 2 |
| Gate-Source Charge | Qgs |  | 5 |  | nC |  | 2 |
| Gate-Drain Charge | Qgd |  | 5 |  | nC |  | 2 |

## CAD (KiCad official)

- Symbol: `WSP6956`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `wsp6956-etched.step` / `wsp6956-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `wsp6956.step` / `wsp6956.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Winsok Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915951417380864) (7 pp, sha256 `b71122c5c4a98b46`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/wsp6956-datasheet.pdf)