PCB Design Rules

(version 1)

# JLCPCB 6-layer design rules (standard process)
# 
# Min trace width: 0.09 mm (3.5 mil) - 1 oz copper outer layer, 3 mil acceptable in BGA fan-outs
# Min spacing: 0.09 mm (3.5 mil) - 1 oz copper, different nets
# Min drill: 0.15 mm (5.91 mil)
# Min via: 0.15 mm hole / 0.25 mm pad
# Annular ring: via 0.15 mm
# Copper to board edge: 0.2 mm
# Hole to hole: 0.2 mm
# Board thickness options: 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, 2.0 mm
# Copper weight options: 1 oz, 2 oz
# Surface finishes: ENIG
# Max board size: 656 x 586 mm
# 
# Same source page as 2 layer, multilayer column. 6 layer and above boards only have ENIG surface finish. Via-in-pad epoxy filled and capped is the default process for 6 layer and above boards, compatible with via diameters 0.15 to 0.55 mm. 2 oz outer: min trace/spacing 0.15/0.15 mm (6/6 mil). Backdrill supported on 4 to 32 layer FR4, thickness 0.8 mm or more.
# 
# Sources:
# - https://jlcpcb.com/capabilities/pcb-capabilities (read 2026-09-03)

(rule "min-track-width"
  (constraint track_width (min 0.09mm))
  (layer "*.Cu")
  (condition "A.type == 'track'"))

(rule "min-clearance"
  (constraint clearance (min 0.09mm))
  (condition "A.type == 'track' && B.type == 'track'"))

(rule "min-hole"
  (constraint hole (min 0.15mm))
  (condition "A.type == 'pad' || A.type == 'via'"))

(rule "min-via-diameter"
  (constraint via_diameter (min 0.25mm))
  (condition "A.type == 'via'"))

(rule "min-edge-clearance"
  (constraint edge_clearance (min 0.2mm))
  (condition "A.type == 'track'"))

(rule "min-silk-thickness"
  (constraint text_thickness (min 0.15mm))
  (layer "*.SilkS")
  (condition "A.type == 'text' || A.type == 'graphic'"))

# JLCPCB lists 1.0 mm; Adom has tested 0.8 mm and it prints legibly (2026-10-08).
(rule "min-silk-text-height"
  (constraint text_height (min 0.8mm))
  (layer "*.SilkS")
  (condition "A.type == 'text'"))