PCB Design Rules - kicad/jlcpcb-6L.board-setup.json

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

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John Lauer Silkscreen text minimums: 3rdPartyFab 0.5 mm, JLCPCB 0.8 mm (Adom-tested) 437f71a 12d ago

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{
  "vendor": "JLCPCB",
  "process": "standard",
  "layerCount": 6,
  "boardSetupConstraints": {
    "minTrackWidthMm": 0.09,
    "minClearanceMm": 0.09,
    "minViaDrillMm": 0.15,
    "minViaDiameterMm": 0.25,
    "minHoleMm": 0.15,
    "copperEdgeClearanceMm": 0.2,
    "holeToHoleMm": 0.2,
    "annularRingViaMm": 0.15,
    "annularRingPadMm": null,
    "silkMinLineWidthMm": 0.15,
    "silkMinTextHeightMm": 0.8,
    "maskExpansionMm": 0.0
  },
  "notes": "Apply as Board Setup, Constraints. The matching .kicad_dru file carries the same limits as custom rules; the two are redundant on purpose so both the GUI constraints and kicad-cli DRC enforce them.",
  "sources": [
    {
      "url": "https://jlcpcb.com/capabilities/pcb-capabilities",
      "dateRead": "2026-09-03"
    }
  ]
}