skill

PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

pcbdesign-rulesdrcfabricationjlcpcbpcbwayfusionkicadaltiumedrukicad_dru
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History of fusion/osh-park-2L.edru

2 commits ← Back to file
generate.py: emit the Same-net track spacing rule disabled (it flags every trace joint as an Overlap warning); regenera…
John Lauer · 0f50312 · 1mo ago
Initial publish: canonical per-vendor PCB fab design rules. 13 vendors, 56 records (vendor, process, layer count) read…
John Lauer · bafc3ce · 1mo ago