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PCB Design Rules

Public Made by Adom

by adom

Canonical PCB fab design rules (DRC) for every popular vendor: one JSON record per vendor, process and layer count, with generated Fusion/EAGLE .dru and .edru, KiCad .kicad_dru plus board-setup JSON, Altium .RUL exports, and a human comparison table. Every number cites the vendor's own capabilities page and the date it was read.

pcbdesign-rulesdrcfabricationjlcpcbpcbwayfusionkicadaltiumedrukicad_dru
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Delete altium/adom-instapcb-4L.RUL

John Lauer ·8175e48a19 ·14d ago ·parent 207b0fb
1 file changed −44
altium/adom-instapcb-4L.RUL−44
altium/adom-instapcb-4L.RULdeleted−44
@@ -1,44 +0,0 @@-[Design Rules]-RuleCount=6--[Rule1]-RuleKind=Width-RuleName=MinTraceWidth-Scope1=All-Scope2=-Attribute=MinWidth=0.09mm|PreferredWidth=0.18mm|MaxWidth=25.4mm--[Rule2]-RuleKind=Clearance-RuleName=MinClearance-Scope1=All-Scope2=-Attribute=Clearance=0.09mm--[Rule3]-RuleKind=RoutingViaStyle-RuleName=MinVia-Scope1=All-Scope2=-Attribute=PreferredViaWidth=0.25mm|PreferredViaHoleWidth=0.15mm|MinViaWidth=0.25mm|MaxViaWidth=6.35mm|MinViaHoleWidth=0.15mm|MaxViaHoleWidth=6.35mm--[Rule4]-RuleKind=HoleSize-RuleName=MinHole-Scope1=All-Scope2=-Attribute=HoleWidth=0.15mm--[Rule5]-RuleKind=AnnularRing-RuleName=MinAnnularRing-Scope1=All-Scope2=-Attribute=MinAnnularRing=0.1mm--[Rule6]-RuleKind=BoardOutlineClearance-RuleName=CopperToBoardEdge-Scope1=All-Scope2=-Attribute=Clearance=0.2mm