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Microchip Tech Ethernet ICs, VQFN-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LAN7431T-V

Microchip Tech · Ethernet ICs · VQFN-72(10x10)

LAN7431T-V from Microchip Tech, in a VQFN-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDDH_1	power_in	Analog I/O supply of 2.5V or 3.3V that powers the bandgap reference and crystal oscillator amplifier on LAN7431.
2	AVDDL_1	power_in	1.2V power for the analog core.
3	VDDVARIO_B	power_in	1.8V to 3.3V variable supply for the RGMII and MII related I/Os.
4	TXD3	output	Transmit data bit 3 from the MAC to the external Ethernet PHY, used in RGMII and MII modes.
5	TXD2	output	Transmit data bit 2 from the MAC to the external Ethernet PHY, used in RGMII and MII modes.
6	TXD1	output	Transmit data bit 1 from the MAC to the external Ethernet PHY, used in RGMII and MII modes.
7	VDDVARIO_B	power_in	1.8V to 3.3V variable supply for the RGMII and MII related I/Os.
8	TXD0	output	Transmit data bit 0 from the MAC to the external Ethernet PHY, used in RGMII and MII modes.
9	TX_ER/MII_EN	output	In MII mode it is the transmit error output to the external PHY; as the MII_EN strap, high selects MII mode and low or floating selects RGMII mode.
10	TX_CTL/TX_EN	output	RGMII transmit control (TXEN/TXER) or MII transmit enable indicating valid data on TXD[3:0].
11	TXC/TX_CLK	output	RGMII transmit reference clock output (125/25/2.5 MHz for 1000/100/10 Mbps) or, in MII mode, the TX_CLK input (25 MHz at 100BASE-TX, 2.5 MHz at 10BASE-T).
12	VDDVARIO_B	power_in	1.8V to 3.3V variable supply for the RGMII and MII related I/Os. The datasheet Table 3-2 prints this as VDDVADIO_B; VDDVARIO_B is used here to match the pin diagram and Table 3-3.
13	RXC/RX_CLK	input	RGMII receive clock from the external PHY (125/25/2.5 MHz for 1000/100/10 Mbps) or the MII RX_CLK input (25 MHz at 100BASE-TX, 2.5 MHz at 10BASE-T).
14	RX_CTL/RX_DV	input	RGMII receive control input carrying RXDV and RXER, or the MII receive data valid input.
15	RXD0	input	Receive data bit 0 from the external Ethernet PHY to the MAC in RGMII and MII modes.
16	RXD1	input	Receive data bit 1 from the external Ethernet PHY to the MAC in RGMII and MII modes.
17	RXD2	input	Receive data bit 2 from the external Ethernet PHY to the MAC in RGMII and MII modes.
18	RXD3	input	Receive data bit 3 from the external Ethernet PHY to the MAC in RGMII and MII modes.
19	VDDVARIO_B	power_in	1.8V to 3.3V variable supply for the RGMII and MII related I/Os.
20	CLK125/RX_ER	input	125 MHz clock input from the external PHY, which may generate the RGMII TX clock; in MII mode it is the RX_ER receive error input.
21	REFCLK_25/GPIO11	output	25 MHz reference clock output to the external Ethernet PHY (VO12), also configurable as GPIO11.
22	COL/GPIO10	input	MII collision detect input from the external PHY, used in half-duplex mode only, also configurable as GPIO10.
23	CRS	input	MII carrier sense input from the external PHY, used in half-duplex mode only.
24	VDD12CORE	power_in	1.2V digital core power input.
25	VP	power_in	1.2V PCIe PHY analog and digital power.
26	GD_1	power_in	PCIe ground pin.
27	PCIE_RX_P	input	PCIe differential serial data input, positive, for the 2.5 GT/s link.
28	PCIE_RX_M	input	PCIe differential serial data input, negative, for the 2.5 GT/s link.
29	GD_2	power_in	PCIe ground pin.
30	PCIE_TX_P	output	PCIe differential serial data output, positive, for the 2.5 GT/s link; a series capacitor of 100nF to 200nF is required.
31	VPTX	power_in	1.2V PCIe PHY transmit power.
32	PCIE_TX_M	output	PCIe differential serial data output, negative, for the 2.5 GT/s link; a series capacitor of 100nF to 200nF is required.
33	GD_3	power_in	PCIe ground pin.
34	VPH	power_in	2.5V PCIe PHY power.
35	RESREF	passive	Reference resistor pin, connected to ground through a 200 ohm 1%, 100 ppm/°C resistor.
36	PCIE_CLK_P	input	PCIe differential 100 MHz reference clock input, positive.
37	PCIE_CLK_M	input	PCIe differential 100 MHz reference clock input, negative.
38	VDD25_REG_OUT	power_out	2.5V output of the integrated LDO used to supply the PCIe PHY.
39	VDD_REG_IN	power_in	3.3V input supply to the integrated LDO; if a 2.5V supply is used it must be externally connected to VDD25_REG_OUT.
40	DUPLEX	input	Duplex mode input from the external PHY; high means full duplex, and it should be tied to VDDVARIO if the PHY has no duplex output.
41	PHY_INT_N	input	Interrupt input from the external Ethernet PHY.
42	PHY_RESET_N	output	Reset output to the external Ethernet PHY (VO12).
43	VDDVARIO	power_in	1.8V to 3.3V variable supply for the I/Os (Group A).
44	RESET_N	input	Active-low system reset input; if unused it must be pulled up to VDDVARIO.
45	TEST	input	Test mode enable pin that must be connected to ground for proper functional operation.
46	VDD12CORE	power_in	1.2V digital core power input.
47	GPIO9/TCK	bidirectional	Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up), also the JTAG test clock TCK, whose maximum frequency is half the system clock.
48	VDDVARIO	power_in	1.8V to 3.3V variable supply for the I/Os (Group A).
49	GPIO8/TDI	bidirectional	Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up), also the JTAG test data input TDI.
50	GPIO7/TMS	bidirectional	Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up), also the JTAG test mode select TMS.
51	VDD12_SW_OUT	power_out	1.2V output voltage from the integrated switching regulator.
52	VDD_SW_IN	power_in	1.8V to 3.3V input voltage for the switching regulator.
53	VDD12_SW_FB	power_in	Feedback pin for the integrated switching regulator; tie to VDD_SW_IN to disable the regulator.
54	GPIO6/TDO	bidirectional	Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up), also the JTAG test data output TDO (VO12).
55	GPIO5	bidirectional	Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up).
56	GPIO4	bidirectional	Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up).
57	VAUX_DET/GPIO3	input	Auxiliary voltage detect; tie to VSS if PME from D3cold is not supported, or to 3.3V auxiliary voltage if it is, also configurable as GPIO3.
58	EECLK/GPIO2/ADV_PM_DISABLE	bidirectional	EEPROM clock output to the external EEPROM (VO12, held low during reset), also GPIO2; as the ADV_PM_DISABLE strap, high defaults the listed PCIe power management bits low.
59	EEDIO/GPIO1	bidirectional	EEPROM bidirectional data pin, which needs an external resistor on the EEPROM data output to prevent contention; also GPIO1.
60	EECS/GPIO0	bidirectional	EEPROM chip select output (VO12), held low during reset by an internal pull-down, also GPIO0.
61	VDDVARIO	power_in	1.8V to 3.3V variable supply for the I/Os (Group A).
62	VDD12CORE	power_in	1.2V digital core power input.
63	MDIO	bidirectional	Management data to and from the external Ethernet PHY; an external pull-up is required when the MII management interface is used.
64	MDC	output	Management clock output to the external Ethernet PHY (VO8).
65	VDD_OTP	power_in	3.3V supply to the OTP charge pump.
66	CLKREQ#	bidirectional	Open-drain PCIe clock request signal used for link clock power management and L1 substate control.
67	WAKE#	bidirectional	Open-drain PCIe wake signal, driven low when the device detects a wakeup; in OBFF mode it is used as an input.
68	PERST#	input	PCIe power and clock good input indicating that PCIe power and clock are available.
69	AVDD12	power_in	1.2V power for the PLL/DLL.
70	XO	output	Crystal output, connected to one lead of a 25 MHz crystal; not connected when an oscillator or external clock is used.
71	XI	input	Crystal/oscillator input for a 25 MHz crystal or a 3.3V oscillator or external clock, with ±50ppm tolerance.
72	ISET	passive	External PHY bias resistor pin, connected to ground through a 6.04K 1% resistor.
73	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	VQFN-72(10x10)
Category	Communication Interface Chip/UART/485/232
Pins	73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDDVARIO, VDDVARIO_B, VDD_SW_IN, VDD_REG_IN, VDD_OTP)		-0.5		4.6	V	Note 7-1	48
+2.5 V PCIe PHY Analog Supply Voltage (VPH)	VPH	-0.5		3.2	V	Note 7-1	48
+1.2 V Analog Supply Voltage (VPTX, VP; also listed with AVDD12, AVDDL_1, AVDDL_2)	VPTX, VP	-0.5		1.5	V	Note 7-1	48
+1.2 V Digital Supply Voltage	VDD12CORE	-0.5		1.5	V	Note 7-1	48
Positive voltage on input signal pins, with respect to ground				4.6	V		48
Negative voltage on input signal pins, with respect to ground		-0.5			V		48
Storage Temperature		-65		150	°C		48
HBM ESD Performance		-2		2	kV	HBM	48
Supply Voltage (VDD_SW_IN)	VDD_SW_IN	1.62		3.63	V		48
Supply Voltage (VDDVARIO, VDDVARIO_B)	VDDVARIO	1.62		3.63	V		48
Supply Voltage (VDD_REG_IN, VDD_OTP)	VDD_REG_IN, VDD_OTP	2.97		3.63	V		48
+2.5 V PCIe PHY Analog Supply Voltage (VPH)	VPH	2.33		2.75	V		48
+1.2 V PCIe PHY Analog Supply Voltage (VPTX, VP)	VPTX, VP	1.12		1.32	V		48
Digital Supply Voltage	VDD12CORE	1.14		1.32	V		48
Positive voltage on input signal pins, with respect to ground (operating)				3.63	V		48
Negative voltage on input signal pins, with respect to ground (operating)		-0.3			V		48
Ambient Operating Temperature in Still Air, commercial version	TA	0		70	°C	Commercial version (Note 7-3)	48
Ambient Operating Temperature in Still Air, industrial version	TA	-40		85	°C	Industrial version (Note 7-3)	48
Ambient Operating Temperature in Still Air, automotive version	TA	-40		105	°C	Automotive version (Note 7-3)	48
Low Input Level (IS type)	VIL			0.8	V	Schmitt trigger	52
High Input Level (IS type)	VIH	2			V	Schmitt trigger	52
Schmitt Trigger Hysteresis (IS type)	VHYS	100		245	mV	Schmitt trigger	52
Input Leakage (IS type)	IIH	-10		10	µA	VIN = VSS or VDD_OTP; Note 7-4	52
Input Capacitance (IS type)	CIN			3	pF	Note 7-4	52
Low Output Level (OD4 type)	VOL			0.2	V	IOL = -4 mA	52
Low Input Level (ICLK type)	VIL			0.5	V	Note 7-5	52
High Input Level (ICLK type)	VIH	2			V	Note 7-5	52
Input Leakage (ICLK type)	IIH	-10		10	µA	Note 7-5	52
Schmitt Trigger Hysteresis (VIS type)	VHYS	100		245	mV	Schmitt trigger	53
Input Leakage (VIS type)	IIH	-10		10	µA	VIN = VSS or VDDVARIO; Note 7-6	53
Input Capacitance (VIS type)	CIN			3	pF	Note 7-6	53
Low Output Level (VO8 type)	VOL			0.4	V	IOL = -8 mA	53
Low Output Level (VOD8 type)	VOL			0.4	V	IOL = -8 mA	53
Low Output Level (VO12 type)	VOL			0.4	V	IOL = -12 mA	53
Low Output Level (VOD12 type)	VOL			0.4	V	IOL = -12 mA	53
Input Leakage (RGMII_I type)	IIH	-15		15	µA	VIN = VSS or VDDVARIO; Note 7-6	54
Input Capacitance (RGMII_I type)	CIN			3	pF	Note 7-6	54
Schmitt Trigger Hysteresis (RGMII_I type)	VHYS	58		150	mV	Schmitt trigger	54
Low Output Level (RGMII_O type)	VOL			0.4	V	IOL = -6 mA	54
Output Impedance (RGMII_O type)	RO	50	50	50	Ω		54
Receiver Input Leakage (terminations off)	III			2	µA	Terminations off	55
Transmitter Input Leakage	III			25	µA		55
PCIe Clock Input Leakage	III			32	nA		55
Power supply turn on time	tpon			50	ms		57
Power supply turn off time	tpoff			500	ms		57
Configuration strap hold after external power supply at operational level	tcsh	22			ms		57
Output drive after straps latched	todad			3	µs		57
RESET_N input assertion time	trstia	1			µs		58
Configuration strap setup before RESET_N deassertion	tcss	200			ns		58
Configuration strap hold after RESET_N deassertion	tcsh	10			ns		58
Output drive after RESET_N deassertion	todad			3	µs		58
Junction-to-ambient thermal resistance (72-SQFN)	JA		20.6		°C/W	0 m/s air velocity	49
Junction-to-ambient thermal resistance (72-SQFN)	JA		18		°C/W	1 m/s air velocity	49
Junction-to-top characterization parameter (72-SQFN)	JT		0.1		°C/W	0 m/s air velocity	49
Junction-to-top characterization parameter (72-SQFN)	JT		0.2		°C/W	1 m/s air velocity	49
Junction-to-case thermal resistance (72-SQFN)	JC		1.6		°C/W	N/A	49

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	ppa		• Energy Efficient Ethernet (EEE) Support with Low-Power Idle (LPI) Mode and Clock Stoppage for 100BASE-TX/	35

CAD (KiCad official)

Symbol: LAN7431T-V
Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
3D model: VQFN-72(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: lan7431t-v-etched.step / lan7431t-v-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan7431t-v.step / lan7431t-v.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (77 pp, sha256 ad01b0713999a060, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LAN7431T-V

Verified LAN7431T-V

Verification log 1 record

LAN7431T-V

Pinout

Key specifications

Electrical characteristics

Materials and finish

CAD (KiCad official)

Provenance