component
LAN7431T-V
Public Made by Adomby adom
Microchip Tech Ethernet ICs, VQFN-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "lan7431t-v",
"title": "LAN7431T-V",
"brief": "Microchip Tech Ethernet ICs, VQFN-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"communication interface chip-uart-485-232",
"lan7431t-v",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "LAN7431T-V",
"manufacturer": "Microchip Tech",
"package": "VQFN-72(10x10)",
"pin_count": 73,
"category": "Communication Interface Chip/UART/485/232",
"subcategory": "Ethernet ICs",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/3aae0fa39559c93683db0bdc8262e5dd.pdf",
"parts": {
"symbol": "lan7431t-v.kicad_sym",
"footprint": "lan7431t-v.kicad_mod",
"model_3d": "lan7431t-v-hero.glb",
"model_3d_plain": "lan7431t-v-etched.glb",
"model_3d_step": "lan7431t-v-etched.step",
"model_3d_step_plain": "lan7431t-v.step",
"lbr": "lan7431t-v.lbr"
},
"distributor_links": {
"lcsc": "C625076"
},
"distributor_check": {
"checked_at": "2026-10-30T16:01:03Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "AVDDH_1",
"type": "power_in",
"description": "Analog I/O supply of 2.5V or 3.3V that powers the bandgap reference and crystal oscillator amplifier on LAN7431."
},
{
"number": "2",
"name": "AVDDL_1",
"type": "power_in",
"description": "1.2V power for the analog core."
},
{
"number": "3",
"name": "VDDVARIO_B",
"type": "power_in",
"description": "1.8V to 3.3V variable supply for the RGMII and MII related I/Os."
},
{
"number": "4",
"name": "TXD3",
"type": "output",
"description": "Transmit data bit 3 from the MAC to the external Ethernet PHY, used in RGMII and MII modes."
},
{
"number": "5",
"name": "TXD2",
"type": "output",
"description": "Transmit data bit 2 from the MAC to the external Ethernet PHY, used in RGMII and MII modes."
},
{
"number": "6",
"name": "TXD1",
"type": "output",
"description": "Transmit data bit 1 from the MAC to the external Ethernet PHY, used in RGMII and MII modes."
},
{
"number": "7",
"name": "VDDVARIO_B",
"type": "power_in",
"description": "1.8V to 3.3V variable supply for the RGMII and MII related I/Os."
},
{
"number": "8",
"name": "TXD0",
"type": "output",
"description": "Transmit data bit 0 from the MAC to the external Ethernet PHY, used in RGMII and MII modes."
},
{
"number": "9",
"name": "TX_ER/MII_EN",
"type": "output",
"description": "In MII mode it is the transmit error output to the external PHY; as the MII_EN strap, high selects MII mode and low or floating selects RGMII mode."
},
{
"number": "10",
"name": "TX_CTL/TX_EN",
"type": "output",
"description": "RGMII transmit control (TXEN/TXER) or MII transmit enable indicating valid data on TXD[3:0]."
},
{
"number": "11",
"name": "TXC/TX_CLK",
"type": "output",
"description": "RGMII transmit reference clock output (125/25/2.5 MHz for 1000/100/10 Mbps) or, in MII mode, the TX_CLK input (25 MHz at 100BASE-TX, 2.5 MHz at 10BASE-T)."
},
{
"number": "12",
"name": "VDDVARIO_B",
"type": "power_in",
"description": "1.8V to 3.3V variable supply for the RGMII and MII related I/Os. The datasheet Table 3-2 prints this as VDDVADIO_B; VDDVARIO_B is used here to match the pin diagram and Table 3-3."
},
{
"number": "13",
"name": "RXC/RX_CLK",
"type": "input",
"description": "RGMII receive clock from the external PHY (125/25/2.5 MHz for 1000/100/10 Mbps) or the MII RX_CLK input (25 MHz at 100BASE-TX, 2.5 MHz at 10BASE-T)."
},
{
"number": "14",
"name": "RX_CTL/RX_DV",
"type": "input",
"description": "RGMII receive control input carrying RXDV and RXER, or the MII receive data valid input."
},
{
"number": "15",
"name": "RXD0",
"type": "input",
"description": "Receive data bit 0 from the external Ethernet PHY to the MAC in RGMII and MII modes."
},
{
"number": "16",
"name": "RXD1",
"type": "input",
"description": "Receive data bit 1 from the external Ethernet PHY to the MAC in RGMII and MII modes."
},
{
"number": "17",
"name": "RXD2",
"type": "input",
"description": "Receive data bit 2 from the external Ethernet PHY to the MAC in RGMII and MII modes."
},
{
"number": "18",
"name": "RXD3",
"type": "input",
"description": "Receive data bit 3 from the external Ethernet PHY to the MAC in RGMII and MII modes."
},
{
"number": "19",
"name": "VDDVARIO_B",
"type": "power_in",
"description": "1.8V to 3.3V variable supply for the RGMII and MII related I/Os."
},
{
"number": "20",
"name": "CLK125/RX_ER",
"type": "input",
"description": "125 MHz clock input from the external PHY, which may generate the RGMII TX clock; in MII mode it is the RX_ER receive error input."
},
{
"number": "21",
"name": "REFCLK_25/GPIO11",
"type": "output",
"description": "25 MHz reference clock output to the external Ethernet PHY (VO12), also configurable as GPIO11."
},
{
"number": "22",
"name": "COL/GPIO10",
"type": "input",
"description": "MII collision detect input from the external PHY, used in half-duplex mode only, also configurable as GPIO10."
},
{
"number": "23",
"name": "CRS",
"type": "input",
"description": "MII carrier sense input from the external PHY, used in half-duplex mode only."
},
{
"number": "24",
"name": "VDD12CORE",
"type": "power_in",
"description": "1.2V digital core power input."
},
{
"number": "25",
"name": "VP",
"type": "power_in",
"description": "1.2V PCIe PHY analog and digital power."
},
{
"number": "26",
"name": "GD_1",
"type": "power_in",
"description": "PCIe ground pin."
},
{
"number": "27",
"name": "PCIE_RX_P",
"type": "input",
"description": "PCIe differential serial data input, positive, for the 2.5 GT/s link."
},
{
"number": "28",
"name": "PCIE_RX_M",
"type": "input",
"description": "PCIe differential serial data input, negative, for the 2.5 GT/s link."
},
{
"number": "29",
"name": "GD_2",
"type": "power_in",
"description": "PCIe ground pin."
},
{
"number": "30",
"name": "PCIE_TX_P",
"type": "output",
"description": "PCIe differential serial data output, positive, for the 2.5 GT/s link; a series capacitor of 100nF to 200nF is required."
},
{
"number": "31",
"name": "VPTX",
"type": "power_in",
"description": "1.2V PCIe PHY transmit power."
},
{
"number": "32",
"name": "PCIE_TX_M",
"type": "output",
"description": "PCIe differential serial data output, negative, for the 2.5 GT/s link; a series capacitor of 100nF to 200nF is required."
},
{
"number": "33",
"name": "GD_3",
"type": "power_in",
"description": "PCIe ground pin."
},
{
"number": "34",
"name": "VPH",
"type": "power_in",
"description": "2.5V PCIe PHY power."
},
{
"number": "35",
"name": "RESREF",
"type": "passive",
"description": "Reference resistor pin, connected to ground through a 200 ohm 1%, 100 ppm/°C resistor."
},
{
"number": "36",
"name": "PCIE_CLK_P",
"type": "input",
"description": "PCIe differential 100 MHz reference clock input, positive."
},
{
"number": "37",
"name": "PCIE_CLK_M",
"type": "input",
"description": "PCIe differential 100 MHz reference clock input, negative."
},
{
"number": "38",
"name": "VDD25_REG_OUT",
"type": "power_out",
"description": "2.5V output of the integrated LDO used to supply the PCIe PHY."
},
{
"number": "39",
"name": "VDD_REG_IN",
"type": "power_in",
"description": "3.3V input supply to the integrated LDO; if a 2.5V supply is used it must be externally connected to VDD25_REG_OUT."
},
{
"number": "40",
"name": "DUPLEX",
"type": "input",
"description": "Duplex mode input from the external PHY; high means full duplex, and it should be tied to VDDVARIO if the PHY has no duplex output."
},
{
"number": "41",
"name": "PHY_INT_N",
"type": "input",
"description": "Interrupt input from the external Ethernet PHY."
},
{
"number": "42",
"name": "PHY_RESET_N",
"type": "output",
"description": "Reset output to the external Ethernet PHY (VO12)."
},
{
"number": "43",
"name": "VDDVARIO",
"type": "power_in",
"description": "1.8V to 3.3V variable supply for the I/Os (Group A)."
},
{
"number": "44",
"name": "RESET_N",
"type": "input",
"description": "Active-low system reset input; if unused it must be pulled up to VDDVARIO."
},
{
"number": "45",
"name": "TEST",
"type": "input",
"description": "Test mode enable pin that must be connected to ground for proper functional operation."
},
{
"number": "46",
"name": "VDD12CORE",
"type": "power_in",
"description": "1.2V digital core power input."
},
{
"number": "47",
"name": "GPIO9/TCK",
"type": "bidirectional",
"description": "Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up), also the JTAG test clock TCK, whose maximum frequency is half the system clock."
},
{
"number": "48",
"name": "VDDVARIO",
"type": "power_in",
"description": "1.8V to 3.3V variable supply for the I/Os (Group A)."
},
{
"number": "49",
"name": "GPIO8/TDI",
"type": "bidirectional",
"description": "Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up), also the JTAG test data input TDI."
},
{
"number": "50",
"name": "GPIO7/TMS",
"type": "bidirectional",
"description": "Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up), also the JTAG test mode select TMS."
},
{
"number": "51",
"name": "VDD12_SW_OUT",
"type": "power_out",
"description": "1.2V output voltage from the integrated switching regulator."
},
{
"number": "52",
"name": "VDD_SW_IN",
"type": "power_in",
"description": "1.8V to 3.3V input voltage for the switching regulator."
},
{
"number": "53",
"name": "VDD12_SW_FB",
"type": "power_in",
"description": "Feedback pin for the integrated switching regulator; tie to VDD_SW_IN to disable the regulator."
},
{
"number": "54",
"name": "GPIO6/TDO",
"type": "bidirectional",
"description": "Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up), also the JTAG test data output TDO (VO12)."
},
{
"number": "55",
"name": "GPIO5",
"type": "bidirectional",
"description": "Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up)."
},
{
"number": "56",
"name": "GPIO4",
"type": "bidirectional",
"description": "Programmable GPIO (push-pull, open-drain, or Schmitt input with pull-up)."
},
{
"number": "57",
"name": "VAUX_DET/GPIO3",
"type": "input",
"description": "Auxiliary voltage detect; tie to VSS if PME from D3cold is not supported, or to 3.3V auxiliary voltage if it is, also configurable as GPIO3."
},
{
"number": "58",
"name": "EECLK/GPIO2/ADV_PM_DISABLE",
"type": "bidirectional",
"description": "EEPROM clock output to the external EEPROM (VO12, held low during reset), also GPIO2; as the ADV_PM_DISABLE strap, high defaults the listed PCIe power management bits low."
},
{
"number": "59",
"name": "EEDIO/GPIO1",
"type": "bidirectional",
"description": "EEPROM bidirectional data pin, which needs an external resistor on the EEPROM data output to prevent contention; also GPIO1."
},
{
"number": "60",
"name": "EECS/GPIO0",
"type": "bidirectional",
"description": "EEPROM chip select output (VO12), held low during reset by an internal pull-down, also GPIO0."
},
{
"number": "61",
"name": "VDDVARIO",
"type": "power_in",
"description": "1.8V to 3.3V variable supply for the I/Os (Group A)."
},
{
"number": "62",
"name": "VDD12CORE",
"type": "power_in",
"description": "1.2V digital core power input."
},
{
"number": "63",
"name": "MDIO",
"type": "bidirectional",
"description": "Management data to and from the external Ethernet PHY; an external pull-up is required when the MII management interface is used."
},
{
"number": "64",
"name": "MDC",
"type": "output",
"description": "Management clock output to the external Ethernet PHY (VO8)."
},
{
"number": "65",
"name": "VDD_OTP",
"type": "power_in",
"description": "3.3V supply to the OTP charge pump."
},
{
"number": "66",
"name": "CLKREQ#",
"type": "bidirectional",
"description": "Open-drain PCIe clock request signal used for link clock power management and L1 substate control."
},
{
"number": "67",
"name": "WAKE#",
"type": "bidirectional",
"description": "Open-drain PCIe wake signal, driven low when the device detects a wakeup; in OBFF mode it is used as an input."
},
{
"number": "68",
"name": "PERST#",
"type": "input",
"description": "PCIe power and clock good input indicating that PCIe power and clock are available."
},
{
"number": "69",
"name": "AVDD12",
"type": "power_in",
"description": "1.2V power for the PLL/DLL."
},
{
"number": "70",
"name": "XO",
"type": "output",
"description": "Crystal output, connected to one lead of a 25 MHz crystal; not connected when an oscillator or external clock is used."
},
{
"number": "71",
"name": "XI",
"type": "input",
"description": "Crystal/oscillator input for a 25 MHz crystal or a 3.3V oscillator or external clock, with ±50ppm tolerance."
},
{
"number": "72",
"name": "ISET",
"type": "passive",
"description": "External PHY bias resistor pin, connected to ground through a 6.04K 1% resistor."
},
{
"number": "73",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Package naming: the datasheet calls the LAN7431 package a 72-SQFN (10 x 10 mm), not VQFN. The orderi; Table 3-2 prints pin 12 as VDDVADIO_B, but the pin diagram and Table 3-3 use VDDVARIO_B. VDDVARIO_B ; Exposed pad (VSS) on the bottom of the package has no pin number in the datasheet and is not listed.",
"exposed pad 73 added from the footprint",
"50/73 pins cited to the wrong page (name found elsewhere): ['9:TX_ER/MII_EN@p23', '12:VDDVARIO_B@p24', '19:VDDVARIO_B@p24', '22:COL/GPIO10@p18']",
"1/73 pin names appear NOWHERE in the datasheet text: ['70:XO@p21']"
],
"pages_sent": 38,
"cost_usd": 0.2114,
"at": "2026-10-30T16:00:12"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/3aae0fa39559c93683db0bdc8262e5dd.pdf",
"pages": 77,
"sha256": "ad01b0713999a060",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 73,
"described": 73,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "lan7431t-v.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.02,
10.02,
0.9
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "5186ca63f89c33f95a063929bd4874c69cc474d86f0ecdd6b3fda2b22ea1b4c9",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "lan7431t-v-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.02,
10.02,
0.9
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "f90a258c5ffc8088c4eab11768c9552b886c701cf33575f1e60215c1ca217c6b",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Microchip Tech",
"Package": "VQFN-72(10x10)",
"Category": "Communication Interface Chip/UART/485/232",
"Pins": "73"
},
"appearance": {
"housing": {
"quote": "• Energy Efficient Ethernet (EEE) Support with Low-Power Idle (LPI) Mode and Clock Stoppage for 100BASE-TX/",
"page": 35,
"doc": "ds.pdf",
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