LAN7431T-V

<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.6.2">
<drawing>
<settings><setting alwaysvectorfont="no"/></settings>
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<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
</layers>
<library>
<description></description>
<packages>
<package name="QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm">
  <description>QFN-72-1EP, 10 x 10 mm, 0.5 mm pitch</description>
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  <text x="0" y="5.975" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>
  <text x="0" y="-5.975" size="1.27" layer="27" align="top-center">&gt;VALUE</text>
</package>
</packages>
<symbols>
<symbol name="LAN7431T-V">
  <wire x1="-12.7" y1="48.26" x2="12.7" y2="48.26" width="0.254" layer="94"/>
  <wire x1="12.7" y1="48.26" x2="12.7" y2="-48.26" width="0.254" layer="94"/>
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  <text x="0.0000" y="50.8000" size="1.27" layer="95" align="center">&gt;NAME</text>
  <text x="0.0000" y="-50.8000" size="1.27" layer="96" align="center">&gt;VALUE</text>
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  <pin name="VDDVARIO_B" x="-17.78" y="40.64" length="middle" direction="pwr"/>
  <pin name="TXD3" x="-17.78" y="38.1" length="middle" direction="out"/>
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  <pin name="TX_ER/MII_EN" x="-17.78" y="25.4" length="middle" direction="out"/>
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  <pin name="TXC/TX_CLK" x="-17.78" y="20.32" length="middle" direction="out"/>
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  <pin name="RXC/RX_CLK" x="-17.78" y="15.24" length="middle" direction="in"/>
  <pin name="RX_CTL/RX_DV" x="-17.78" y="12.7" length="middle" direction="in"/>
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  <pin name="CLK125/RX_ER" x="-17.78" y="-2.54" length="middle" direction="in"/>
  <pin name="REFCLK_25/GPIO11" x="-17.78" y="-5.08" length="middle" direction="out"/>
  <pin name="COL/GPIO10" x="-17.78" y="-7.62" length="middle" direction="in"/>
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  <pin name="EECS/GPIO0" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>
  <pin name="EEDIO/GPIO1" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>
  <pin name="EECLK/GPIO2/ADV_PM_DISABLE" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>
  <pin name="VAUX_DET/GPIO3" x="17.78" y="2.54" length="middle" direction="in" rot="R180"/>
  <pin name="GPIO4" x="17.78" y="0" length="middle" direction="io" rot="R180"/>
  <pin name="GPIO5" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>
  <pin name="GPIO6/TDO" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>
  <pin name="VDD12_SW_FB" x="17.78" y="-7.62" length="middle" direction="pwr" rot="R180"/>
  <pin name="VDD_SW_IN" x="17.78" y="-10.16" length="middle" direction="pwr" rot="R180"/>
  <pin name="VDD12_SW_OUT" x="17.78" y="-12.7" length="middle" direction="out" rot="R180"/>
  <pin name="GPIO7/TMS" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>
  <pin name="GPIO8/TDI" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>
  <pin name="VDDVARIO@2" x="17.78" y="-20.32" length="middle" direction="pwr" rot="R180"/>
  <pin name="GPIO9/TCK" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/>
  <pin name="VDD12CORE@3" x="17.78" y="-25.4" length="middle" direction="pwr" rot="R180"/>
  <pin name="TEST" x="17.78" y="-27.94" length="middle" direction="in" rot="R180"/>
  <pin name="RESET_N" x="17.78" y="-30.48" length="middle" direction="in" rot="R180"/>
  <pin name="VDDVARIO@3" x="17.78" y="-33.02" length="middle" direction="pwr" rot="R180"/>
  <pin name="PHY_RESET_N" x="17.78" y="-35.56" length="middle" direction="out" rot="R180"/>
  <pin name="PHY_INT_N" x="17.78" y="-38.1" length="middle" direction="in" rot="R180"/>
  <pin name="DUPLEX" x="17.78" y="-40.64" length="middle" direction="in" rot="R180"/>
  <pin name="VDD_REG_IN" x="17.78" y="-43.18" length="middle" direction="pwr" rot="R180"/>
  <pin name="VDD25_REG_OUT" x="17.78" y="-45.72" length="middle" direction="out" rot="R180"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="LAN7431T-V" prefix="U">
  <description></description>
  <gates>
    <gate name="G$1" symbol="LAN7431T-V" x="0" y="0"/>
  </gates>
  <devices>
    <device name="" package="QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm">
      <connects>
        <connect gate="G$1" pin="AVDDH_1" pad="1"/>
        <connect gate="G$1" pin="AVDDL_1" pad="2"/>
        <connect gate="G$1" pin="VDDVARIO_B" pad="3"/>
        <connect gate="G$1" pin="TXD3" pad="4"/>
        <connect gate="G$1" pin="TXD2" pad="5"/>
        <connect gate="G$1" pin="TXD1" pad="6"/>
        <connect gate="G$1" pin="VDDVARIO_B@2" pad="7"/>
        <connect gate="G$1" pin="TXD0" pad="8"/>
        <connect gate="G$1" pin="TX_ER/MII_EN" pad="9"/>
        <connect gate="G$1" pin="TX_CTL/TX_EN" pad="10"/>
        <connect gate="G$1" pin="TXC/TX_CLK" pad="11"/>
        <connect gate="G$1" pin="VDDVARIO_B@3" pad="12"/>
        <connect gate="G$1" pin="RXC/RX_CLK" pad="13"/>
        <connect gate="G$1" pin="RX_CTL/RX_DV" pad="14"/>
        <connect gate="G$1" pin="RXD0" pad="15"/>
        <connect gate="G$1" pin="RXD1" pad="16"/>
        <connect gate="G$1" pin="RXD2" pad="17"/>
        <connect gate="G$1" pin="RXD3" pad="18"/>
        <connect gate="G$1" pin="VDDVARIO_B@4" pad="19"/>
        <connect gate="G$1" pin="CLK125/RX_ER" pad="20"/>
        <connect gate="G$1" pin="REFCLK_25/GPIO11" pad="21"/>
        <connect gate="G$1" pin="COL/GPIO10" pad="22"/>
        <connect gate="G$1" pin="CRS" pad="23"/>
        <connect gate="G$1" pin="VDD12CORE" pad="24"/>
        <connect gate="G$1" pin="VP" pad="25"/>
        <connect gate="G$1" pin="GD_1" pad="26"/>
        <connect gate="G$1" pin="PCIE_RX_P" pad="27"/>
        <connect gate="G$1" pin="PCIE_RX_M" pad="28"/>
        <connect gate="G$1" pin="GD_2" pad="29"/>
        <connect gate="G$1" pin="PCIE_TX_P" pad="30"/>
        <connect gate="G$1" pin="VPTX" pad="31"/>
        <connect gate="G$1" pin="PCIE_TX_M" pad="32"/>
        <connect gate="G$1" pin="GD_3" pad="33"/>
        <connect gate="G$1" pin="VPH" pad="34"/>
        <connect gate="G$1" pin="RESREF" pad="35"/>
        <connect gate="G$1" pin="PCIE_CLK_P" pad="36"/>
        <connect gate="G$1" pin="PCIE_CLK_M" pad="37"/>
        <connect gate="G$1" pin="EP" pad="73"/>
        <connect gate="G$1" pin="ISET" pad="72"/>
        <connect gate="G$1" pin="XI" pad="71"/>
        <connect gate="G$1" pin="XO" pad="70"/>
        <connect gate="G$1" pin="AVDD12" pad="69"/>
        <connect gate="G$1" pin="PERST#" pad="68"/>
        <connect gate="G$1" pin="WAKE#" pad="67"/>
        <connect gate="G$1" pin="CLKREQ#" pad="66"/>
        <connect gate="G$1" pin="VDD_OTP" pad="65"/>
        <connect gate="G$1" pin="MDC" pad="64"/>
        <connect gate="G$1" pin="MDIO" pad="63"/>
        <connect gate="G$1" pin="VDD12CORE@2" pad="62"/>
        <connect gate="G$1" pin="VDDVARIO" pad="61"/>
        <connect gate="G$1" pin="EECS/GPIO0" pad="60"/>
        <connect gate="G$1" pin="EEDIO/GPIO1" pad="59"/>
        <connect gate="G$1" pin="EECLK/GPIO2/ADV_PM_DISABLE" pad="58"/>
        <connect gate="G$1" pin="VAUX_DET/GPIO3" pad="57"/>
        <connect gate="G$1" pin="GPIO4" pad="56"/>
        <connect gate="G$1" pin="GPIO5" pad="55"/>
        <connect gate="G$1" pin="GPIO6/TDO" pad="54"/>
        <connect gate="G$1" pin="VDD12_SW_FB" pad="53"/>
        <connect gate="G$1" pin="VDD_SW_IN" pad="52"/>
        <connect gate="G$1" pin="VDD12_SW_OUT" pad="51"/>
        <connect gate="G$1" pin="GPIO7/TMS" pad="50"/>
        <connect gate="G$1" pin="GPIO8/TDI" pad="49"/>
        <connect gate="G$1" pin="VDDVARIO@2" pad="48"/>
        <connect gate="G$1" pin="GPIO9/TCK" pad="47"/>
        <connect gate="G$1" pin="VDD12CORE@3" pad="46"/>
        <connect gate="G$1" pin="TEST" pad="45"/>
        <connect gate="G$1" pin="RESET_N" pad="44"/>
        <connect gate="G$1" pin="VDDVARIO@3" pad="43"/>
        <connect gate="G$1" pin="PHY_RESET_N" pad="42"/>
        <connect gate="G$1" pin="PHY_INT_N" pad="41"/>
        <connect gate="G$1" pin="DUPLEX" pad="40"/>
        <connect gate="G$1" pin="VDD_REG_IN" pad="39"/>
        <connect gate="G$1" pin="VDD25_REG_OUT" pad="38"/>
      </connects>
      <technologies><technology name=""/></technologies>
    </device>
  </devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>