component

CD4011BDRG

Public Made by Adom

by adom

HANSCHIP semiconductor Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4011bdrg
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10 commits ← Back to file
cd4011bdrg: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
Ray · 8d9c9f6 ·
Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout")
Ray · 9467e20 ·
cd4011bdrg: laser-etched CAD + chip hero (factory 2.0.0 backfill)
Ray · 23b8370 ·
cd4011bdrg: stamp component.logic (CD4011) from component-ocean
Ray · bd80da1 ·
cd4011bdrg: backfill missing artifacts (variants)
Ray · 6d74c9b ·
cd4011bdrg: publish the laser-etched STEP alongside the bare one
Ray · 396ee99 ·
Publish 0.2.0
Ray · 4142c66 ·
Set visibility: public
Ray · 4cc0d04 ·
cd4011bdrg: factory component page (tier=lcsc)
Ray · 9a7fa2a ·
Initial commit: component/cd4011bdrg
Ray · 2e35417 ·