CD4011BDRG

@@ -0,0 +1,56 @@+# CD4011BDRG++**HANSCHIP semiconductor** · Gates · SOP-14++CD4011BDRG from HANSCHIP semiconductor, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | I1 | input | Gate 1, input A. CMOS logic input, VIL max 1.5 V @ VDD=5 V; VIH min 3.5 V @ VDD=5 V. Input leakage ±0.3 µA max @ VDD=15 V. |+| 2 | I2 | input | Gate 1, input B. CMOS logic input paired with I1 for the first NAND gate producing O1. |+| 3 | O1 | output | Gate 1 buffered NAND output = NOT(I1 AND I2). VOH ≥ 4.95 V, VOL ≤ 0.05 V @ VDD=5 V, |IO| < 1 µA. |+| 4 | O2 | output | Gate 2 buffered NAND output = NOT(I3 AND I4). Same drive characteristics as O1. |+| 5 | I3 | input | Gate 2, input A. CMOS logic input for the second NAND gate producing O2. |+| 6 | I4 | input | Gate 2, input B. CMOS logic input paired with I3 for the second NAND gate. |+| 7 | VSS | power_in | Ground / negative supply. Reference (0 V) for VDD and all logic signals. |+| 8 | I5 | input | Gate 3, input A. CMOS logic input for the third NAND gate producing O3. |+| 9 | I6 | input | Gate 3, input B. CMOS logic input paired with I5 for the third NAND gate. |+| 10 | O3 | output | Gate 3 buffered NAND output = NOT(I5 AND I6). Same drive characteristics as O1. |+| 11 | O4 | output | Gate 4 buffered NAND output = NOT(I7 AND I8). Same drive characteristics as O1. |+| 12 | I7 | input | Gate 4, input A. CMOS logic input for the fourth NAND gate producing O4. |+| 13 | I8 | input | Gate 4, input B. CMOS logic input paired with I7 for the fourth NAND gate. |+| 14 | VDD | power_in | Positive supply, -0.5 V to +18 V absolute max; recommended 3 V to 15 V. Typical IDD = 7.5 µA max @ 5 V, 30 µA max @ 15 V (Tamb=25 °C). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HANSCHIP semiconductor |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `CD4011BDRG`+- `CD4011BDRGPG`+- `CD4011BDRGPWRG`++## CAD (KiCad official)++- Symbol: `CD4011BDRG`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [HANSCHIP semiconductor datasheet](docs/cd4011bdrg-datasheet.pdf) (10 pp, sha256 `ab85323f2c5d5fc1`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4011bdrg-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "cd4011bdrg",+  "version": "0.1.0",+  "type": "component",+  "description": "HANSCHIP semiconductor Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "cd4011bdrg"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "cd4011bdrg.kicad_sym",+    "cd4011bdrg.kicad_mod",+    "cd4011bdrg.glb",+    "cd4011bdrg.step",+    "cd4011bdrg.lbr",+    "docs/hero.png",+    "docs/cd4011bdrg-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file