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Set visibility: public

Ray ·4cc0d04693 · ·parent 12ebee3
1 file changed +7−4
page.json+7−4
@@ -32,7 +32,7 @@         "number": "1",         "name": "I1",         "type": "input",-        "description": "Gate 1, input A. CMOS logic input, VIL max 1.5 V @ VDD=5 V; VIH min 3.5 V @ VDD=5 V. Input leakage \u00b10.3 \u00b5A max @ VDD=15 V."+        "description": "Gate 1, input A. CMOS logic input, VIL max 1.5 V @ VDD=5 V; VIH min 3.5 V @ VDD=5 V. Input leakage ±0.3 µA max @ VDD=15 V."       },       {         "number": "2",@@ -44,7 +44,7 @@         "number": "3",         "name": "O1",         "type": "output",-        "description": "Gate 1 buffered NAND output = NOT(I1 AND I2). VOH \u2265 4.95 V, VOL \u2264 0.05 V @ VDD=5 V, |IO| < 1 \u00b5A."+        "description": "Gate 1 buffered NAND output = NOT(I1 AND I2). VOH ≥ 4.95 V, VOL ≤ 0.05 V @ VDD=5 V, |IO| < 1 µA."       },       {         "number": "4",@@ -110,7 +110,7 @@         "number": "14",         "name": "VDD",         "type": "power_in",-        "description": "Positive supply, -0.5 V to +18 V absolute max; recommended 3 V to 15 V. Typical IDD = 7.5 \u00b5A max @ 5 V, 30 \u00b5A max @ 15 V (Tamb=25 \u00b0C)."+        "description": "Positive supply, -0.5 V to +18 V absolute max; recommended 3 V to 15 V. Typical IDD = 7.5 µA max @ 5 V, 30 µA max @ 15 V (Tamb=25 °C)."       }     ],     "provenance": {@@ -174,5 +174,8 @@     "docs/cd4011bdrg-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file