CD4011BDRG

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4011bdrg",
  "title": "CD4011BDRG",
  "brief": "HANSCHIP semiconductor Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4011bdrg"
  ],
  "component": {
    "mpn": "CD4011BDRG",
    "manufacturer": "HANSCHIP semiconductor",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312291742_HANSCHIP-semiconductor-CD4011BDRG_C19723781.pdf",
    "parts": {
      "symbol": "cd4011bdrg.kicad_sym",
      "footprint": "cd4011bdrg.kicad_mod",
      "model_3d": "cd4011bdrg-etched.glb",
      "model_3d_plain": "cd4011bdrg.glb",
      "model_3d_step": "cd4011bdrg-etched.step",
      "model_3d_step_plain": "cd4011bdrg.step",
      "lbr": "cd4011bdrg.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "I1",
        "type": "input",
        "description": "Gate 1, input A. CMOS logic input, VIL max 1.5 V @ VDD=5 V; VIH min 3.5 V @ VDD=5 V. Input leakage ±0.3 µA max @ VDD=15 V."
      },
      {
        "number": "2",
        "name": "I2",
        "type": "input",
        "description": "Gate 1, input B. CMOS logic input paired with I1 for the first NAND gate producing O1."
      },
      {
        "number": "3",
        "name": "O1",
        "type": "output",
        "description": "Gate 1 buffered NAND output = NOT(I1 AND I2). VOH ≥ 4.95 V, VOL ≤ 0.05 V @ VDD=5 V, |IO| < 1 µA."
      },
      {
        "number": "4",
        "name": "O2",
        "type": "output",
        "description": "Gate 2 buffered NAND output = NOT(I3 AND I4). Same drive characteristics as O1."
      },
      {
        "number": "5",
        "name": "I3",
        "type": "input",
        "description": "Gate 2, input A. CMOS logic input for the second NAND gate producing O2."
      },
      {
        "number": "6",
        "name": "I4",
        "type": "input",
        "description": "Gate 2, input B. CMOS logic input paired with I3 for the second NAND gate."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground / negative supply. Reference (0 V) for VDD and all logic signals."
      },
      {
        "number": "8",
        "name": "I5",
        "type": "input",
        "description": "Gate 3, input A. CMOS logic input for the third NAND gate producing O3."
      },
      {
        "number": "9",
        "name": "I6",
        "type": "input",
        "description": "Gate 3, input B. CMOS logic input paired with I5 for the third NAND gate."
      },
      {
        "number": "10",
        "name": "O3",
        "type": "output",
        "description": "Gate 3 buffered NAND output = NOT(I5 AND I6). Same drive characteristics as O1."
      },
      {
        "number": "11",
        "name": "O4",
        "type": "output",
        "description": "Gate 4 buffered NAND output = NOT(I7 AND I8). Same drive characteristics as O1."
      },
      {
        "number": "12",
        "name": "I7",
        "type": "input",
        "description": "Gate 4, input A. CMOS logic input for the fourth NAND gate producing O4."
      },
      {
        "number": "13",
        "name": "I8",
        "type": "input",
        "description": "Gate 4, input B. CMOS logic input paired with I7 for the fourth NAND gate."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply, -0.5 V to +18 V absolute max; recommended 3 V to 15 V. Typical IDD = 7.5 µA max @ 5 V, 30 µA max @ 15 V (Tamb=25 °C)."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312291742_HANSCHIP-semiconductor-CD4011BDRG_C19723781.pdf",
        "pages": 10,
        "sha256": "ab85323f2c5d5fc1",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "CD4011",
      "logic_family": "CD4000",
      "function_code": "4011",
      "function_class": "Gate",
      "function_name": "Quad 2-Input NAND Gate",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
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        "file": "cd4011bdrg.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4011bdrg-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
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        "sha256": "e0b2d466a67ebf2113c1ff52d1b97abdfe977a80e7a9f98a94dd8bf53b857585",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "HANSCHIP semiconductor",
      "Package": "SOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4011bdrg"
  ],
  "discovery_pitch": "CD4011BDRG (HANSCHIP semiconductor) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4011bdrg.kicad_sym",
    "cd4011bdrg.kicad_mod",
    "cd4011bdrg.glb",
    "cd4011bdrg.step",
    "cd4011bdrg-etched.step",
    "cd4011bdrg.lbr",
    "docs/hero.png",
    "docs/cd4011bdrg-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "CD4011BDRG",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BDRGPG",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011BDRGPWRG",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T18:37:57.210Z"
}