Design record

How the riser was designed, and where each number came from. The board files, the generators and the raw calculation outputs are in this folder.

What it is

A passive card for the Supermicro AIOM slot. AIOM is Supermicro's name for the OCP NIC 3.0 small form factor (SFF) slot. The card takes the slot's PCIe x16 link and splits it into four x4 links, one per OCuLink 4i (SFF-8611) port. There is no switch or retimer on the card: copper from the gold fingers to the OCuLink pins, plus the small housekeeping circuits the OCP 3.0 spec requires of every card.

Sources

• OCP NIC 3.0 Design Specification v1.6.0: Table 20 (SFF 4C+ pinout), Table 8 (mating order), Table 45 (PRSNTB encoding), Table 47 (REFCLK and PERST# per link), section 4.5.6 (scan chain), section 4.10 (FRU), Fig. 8 to 10 (outline, keep-outs, faceplate grounding).
• SFF-TA-1002 Rev 1.6.2a: Fig. 5-39 and 5-41, the 4C+ card-edge geometry (pad pitch 0.6 mm, 0.38 mm pads, two mating lengths, key positions).
• SFF-9402: Table 6-1, the OCuLink x4 pinout (root-complex side).
• Amphenol drawing G14A421X1BXXXHR rev D: receptacle body and recommended land pattern.
• JLCPCB JLC06161H-3313 stackup as published on jlcpcb.com/impedance (read 2026-10-12).

The card edge and the slot handshake

• Outline. 76 x 115 mm with the SFF ears and latch notch, 2.75 mm copper-free strips along both long edges (the card guides), and all components on the top side (the bottom clearance in the slot is 1.70 mm).
• Fingers. All 168 positions per Table 20, B side on top and A side on the bottom. The GND fingers are the long, first-mate ones (Table 8). Hard gold, 30 degree bevel.
• Bifurcation (present pins). PRSNTB[3:0]# = 0b0011 tells the host this is an "SFF 4C+ 4 x4" card (Table 45): PRSNTB3# and PRSNTB2# are strapped to PRSNTA0# through 100 ohm (the spec allows 0 to 200 ohm); PRSNTB1# and PRSNTB0# are open. A host with BIF = 0b000 then trains 4 x4.
• Scan chain. The spec makes the scan chain mandatory: a 74LV165 (U1) the baseboard clocks out. Inputs A..D carry PRSNTB0..3#, E is WAKE#, F and G (TEMP_WARN, TEMP_CRIT) are tied high (no sensor, never hot), H (FAN_ON_AUX) is tied low. SCAN_CLK has a 1k pull-up, SCAN_LD# 10k up, DATA_OUT 10k down, the last SER 1k up.
• FRU EEPROM. A ROHM BR24H64 (U2, 8 KiB, 2-byte addressing) at 0x50 plus the slot ID (A1 = SLOT_ID0, A2 = SLOT_ID1). The image (fru.bin, 237 bytes used) carries the board and product areas and the OCP Base OEM record (0xC0, IANA 0x00A67F, version 0x06). Write protect is on unless JP1 is bridged.
• NIC_PWR_GOOD. A TPS3808G33 supervisor (U3) watches +3.3 V aux and holds NIC_PWR_GOOD low until it has been above 3.07 V for 20 ms (spec: under 50 ms). Its MR# is AUX_PWR_EN, so power good drops at once when the host turns the slot off.
• PERST#. Each port's PERSTk# goes through a SN74LVC125A buffer (U4) with a 33 ohm series resistor and a 100k pull-down, so a cable plugged into an unpowered slot sees reset held.
• Power. The card draws under 10 mA from +3.3 V aux (limit 1.1 A) and about 2 mA from +12 V (one LED). The OCuLink power pins (A1/A21, "no wire" in OCuLink cables) are not connected.

Stackup and impedance

85 ohm differential (PCIe allows 85 ohm +-15%; the target here is +-10%). Widths are from a 2D finite-difference field solve of the JLC06161H-3313 cross-section (zsolve.py, results in zfinal.json).

Order the board with JLCPCB's impedance control on JLC06161H-3313 and give them these widths.

Routing the 32 lanes

• No AC caps on the riser. The host's TX capacitors are on the baseboard and the device's are on the device (OCP 4.5.1.2). A passive riser must not add a second set.
• Lane reversal. The OCuLink ports face the faceplate, which reverses the lane order inside each port relative to the fingers. The router fixes this with layer changes instead of crossing pairs: lane 0 on L1, lane 1 on L3, lane 2 on L5, lane 3 switching L1 to L5, then two stages of block swaps.
• Vias. Lane 0 TX has none; the others have 2 or 3 per signal. Each signal via has a GND return via within 1.1 mm. The OCuLink pads use via-in-pad (filled and capped, standard on JLC 6-layer).
• Skew. Within every pair the two traces match to 0.017 mm. Across the four lanes of each port and direction, the delays match to 0.01 ps (trace length times the layer's sqrt(eeff) plus the via barrels), with an accordion on lane 0 and bumps on the others.

• REFCLK. Each port gets its own 100 MHz HCSL reference clock pair, passed straight through at 85 ohm.
• Low-speed nets (scan chain, SMBus, PERST#, present pins, power) were routed by a multi-layer maze router with extra clearance (0.28 mm) to the high-speed copper.
• Ground. L2 and L4 are solid planes, the other layers are GND pours, and a 2 mm grid of stitching vias ties them together.

Checks

• DRC (KiCad 10.0.5, JLCPCB 6-layer rule pack from adom/pcb-design-rules, unmodified): 0 errors, 0 unconnected, 0 schematic-parity issues. Four warnings remain: lib_footprint_mismatch on U5 to U8. Moving them through the KiCad bridge dropped the repeated closing vertex of their pin-1 silk polygon; the geometry is unchanged (adom/kicad-bridge#126).
• ERC: 0. The board netlist matches the schematic pin for pin (421 pins, 109 nets).
• Clearance: a container-side check of every routed segment against every other net (check.py): 0 violations.
• Current and heat (adom-fields, 0.1 mm solve over all six layers, explicit stackup): the 0.1 A +3.3 V aux load peaks at 47 A/mm² on a 0.2 mm In4 trace (limit 60). Joule loss is 3 mW and the card rises at most 66 mK in still air. Both DC solves converge (residual under 1e-7). Doing this took a local adom-fields build with 6-layer support and iterative refinement (adom/adom-fields#11); the figures are in docs/analysis/.
• Silkscreen: 48 reference/value fields and 44 texts. A whole-board audit (silk_audit.json: 2199 obstacles, 92 marks): 0 collisions with pads, mask openings, holes or part bodies. Text is at least 0.8 mm with a 0.15 mm stroke (JLC). The values of the dense PERST# resistor block (R11-R14 33, R15-R18 100k) are keyed on the bottom face under the block.
• Manufacturing set (fab/export-check.json): 6 copper Gerbers. 820 plated drill hits (802 vias plus 18 plated pads) and 8 non-plated (the OCuLink pegs), each matching the board. The CPL and the BOM each list exactly the 38 placed parts.

Bench test plan

tests.json lists what to measure on a powered card (on an OCP 3.0 extender, or in the slot with the lid off). Every measurement has a probe spot: TP1 +3.3 V, TP5 +12 V, TP4 SMBus data, TP6 NIC_PWR_GOOD, TP7 to TP10 PERST# of ports 0 to 3, TP11 scan clock, TP12 scan data, and D1/D2 for the camera.

Using it

1. BIOS. Set the AIOM slot's bifurcation to x4x4x4x4. Without it the host trains one x16 link and sees only port 0, or nothing.
2. Cables. Gen4 over OCuLink is short-reach: use good SFF-8611 cables of 0.5 m or less, rated for Gen4.
3. Faceplate. The card follows the SFF outline and the faceplate grounding holes (H1/H2), but the four OCuLink receptacles need a faceplate with matching openings. A plain SFF blank must be cut.
4. FRU. Bridge JP1, write fru.bin (ipmitool fru write <id> fru.bin from the BMC, or i2ctransfer at 0x50 + slot ID from Linux with 2-byte addressing), then open JP1 again.

Files here