board
OCuLink Riser for the Supermicro AIOM Slot
Public Unreviewedby John Lauer
Passive OCP NIC 3.0 SFF card that breaks a Supermicro AIOM slot's PCIe x16 into four OCuLink 4i ports (4 x4, Gen4): 6-layer, 85 ohm, length-matched, DRC-clean KiCad project with Gerbers, BOM and CPL.
main
John Lauer
The finished riser: KiCad project, Gerbers/BOM/CPL, design record, renders and analysis
09d929e
7d ago
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{
"impedance": {
"method": "2D finite-difference Laplace solve (design/zsolve.py), odd/even mode, JLC06161H-3313 published stack (jlcpcb.com/impedance, read 2026-10-12): 3313 prepreg er 4.1 0.0994 mm, 2116 er 4.16 0.1088 mm, core er 4.6 0.55 mm, outer Cu 35 um, inner 15.2 um, solder mask er 3.8",
"target_diff_ohm": 85,
"tolerance_pct": 10,
"L1_microstrip": {
"w": 0.163,
"s": 0.15,
"Zdiff": 85.04,
"eeff_odd": 3.069
},
"L3_stripline": {
"w": 0.131,
"s": 0.15,
"Zdiff": 85.02,
"eeff_odd": 4.311
},
"L5_stripline": {
"w": 0.121,
"s": 0.15,
"Zdiff": 85.17,
"eeff_odd": 4.266
},
"L6_microstrip": {
"w": 0.163,
"s": 0.15,
"note": "same geometry as L1 against L5 GND pour (fan-out zone only)"
}
},
"length_matching": {
"intra_pair_max_skew_mm": 0.0166,
"method": "delay matched per port per direction: trace length x sqrt(eeff_odd)/c per layer plus via barrels; lane 0 (L1 microstrip, no vias) carries an accordion, lanes 1-3 45-degree bumps",
"ports": {
"port0_TX": {
"delays_ps": [
794.15,
794.15,
794.14,
794.15
],
"spread_ps": 0.01
},
"port0_RX": {
"delays_ps": [
819.84,
819.84,
819.84,
819.83
],
"spread_ps": 0.01
},
"port1_TX": {
"delays_ps": [
785.12,
785.12,
785.11,
785.12
],
"spread_ps": 0.01
},
"port1_RX": {
"delays_ps": [
810.82,
810.81,
810.81,
810.81
],
"spread_ps": 0.01
},
"port2_TX": {
"delays_ps": [
786.57,
786.57,
786.57,
786.57
],
"spread_ps": 0.0
},
"port2_RX": {
"delays_ps": [
810.27,
810.26,
810.26,
810.26
],
"spread_ps": 0.01
},
"port3_TX": {
"delays_ps": [
778.68,
778.68,
778.68,
778.68
],
"spread_ps": 0.0
},
"port3_RX": {
"delays_ps": [
806.46,
806.46,
806.45,
806.45
],
"spread_ps": 0.01
}
}
},
"lanes": {
"P00": {
"n": "PETn0",
"p": "PETp0",
"len_n_mm": 135.911,
"len_p_mm": 135.911,
"intra_pair_skew_mm": 0.0,
"delay_ps": 794.15,
"vias_per_signal": 0
},
"R00": {
"n": "PERn0",
"p": "PERp0",
"len_n_mm": 135.336,
"len_p_mm": 135.336,
"intra_pair_skew_mm": 0.0,
"delay_ps": 819.84,
"vias_per_signal": 3
},
"P01": {
"n": "PETn1",
"p": "PETp1",
"len_n_mm": 115.933,
"len_p_mm": 115.933,
"intra_pair_skew_mm": 0.0,
"delay_ps": 794.15,
"vias_per_signal": 2
},
"R01": {
"n": "PERn1",
"p": "PERp1",
"len_n_mm": 119.561,
"len_p_mm": 119.561,
"intra_pair_skew_mm": 0.0,
"delay_ps": 819.84,
"vias_per_signal": 2
},
"P02": {
"n": "PETn2",
"p": "PETp2",
"len_n_mm": 115.069,
"len_p_mm": 115.069,
"intra_pair_skew_mm": 0.0,
"delay_ps": 794.14,
"vias_per_signal": 2
},
"R02": {
"n": "PERn2",
"p": "PERp2",
"len_n_mm": 119.938,
"len_p_mm": 119.938,
"intra_pair_skew_mm": 0.0,
"delay_ps": 819.84,
"vias_per_signal": 2
},
"P03": {
"n": "PETn3",
"p": "PETp3",
"len_n_mm": 115.734,
"len_p_mm": 115.734,
"intra_pair_skew_mm": 0.0,
"delay_ps": 794.15,
"vias_per_signal": 2
},
"R03": {
"n": "PERn3",
"p": "PERp3",
"len_n_mm": 117.949,
"len_p_mm": 117.949,
"intra_pair_skew_mm": 0.0,
"delay_ps": 819.83,
"vias_per_signal": 3
},
"P10": {
"n": "PETn4",
"p": "PETp4",
"len_n_mm": 134.365,
"len_p_mm": 134.365,
"intra_pair_skew_mm": 0.0,
"delay_ps": 785.12,
"vias_per_signal": 0
},
"R10": {
"n": "PERn4",
"p": "PERp4",
"len_n_mm": 133.79,
"len_p_mm": 133.79,
"intra_pair_skew_mm": 0.0,
"delay_ps": 810.82,
"vias_per_signal": 3
},
"P11": {
"n": "PETn5",
"p": "PETp5",
"len_n_mm": 114.532,
"len_p_mm": 114.532,
"intra_pair_skew_mm": -0.0,
"delay_ps": 785.12,
"vias_per_signal": 2
},
"R11": {
"n": "PERn5",
"p": "PERp5",
"len_n_mm": 118.161,
"len_p_mm": 118.161,
"intra_pair_skew_mm": -0.0,
"delay_ps": 810.81,
"vias_per_signal": 2
},
"P12": {
"n": "PETn6",
"p": "PETp6",
"len_n_mm": 113.665,
"len_p_mm": 113.665,
"intra_pair_skew_mm": 0.0,
"delay_ps": 785.11,
"vias_per_signal": 2
},
"R12": {
"n": "PERn6",
"p": "PERp6",
"len_n_mm": 118.534,
"len_p_mm": 118.534,
"intra_pair_skew_mm": 0.0,
"delay_ps": 810.81,
"vias_per_signal": 2
},
"P13": {
"n": "PETn7",
"p": "PETp7",
"len_n_mm": 114.329,
"len_p_mm": 114.329,
"intra_pair_skew_mm": 0.0,
"delay_ps": 785.12,
"vias_per_signal": 2
},
"R13": {
"n": "PERn7",
"p": "PERp7",
"len_n_mm": 116.545,
"len_p_mm": 116.545,
"intra_pair_skew_mm": 0.0,
"delay_ps": 810.81,
"vias_per_signal": 3
},
"P20": {
"n": "PETn8",
"p": "PETp8",
"len_n_mm": 134.613,
"len_p_mm": 134.613,
"intra_pair_skew_mm": -0.0,
"delay_ps": 786.57,
"vias_per_signal": 0
},
"R20": {
"n": "PERn8",
"p": "PERp8",
"len_n_mm": 133.697,
"len_p_mm": 133.697,
"intra_pair_skew_mm": 0.0,
"delay_ps": 810.27,
"vias_per_signal": 3
},
"P21": {
"n": "PETn9",
"p": "PETp9",
"len_n_mm": 114.743,
"len_p_mm": 114.743,
"intra_pair_skew_mm": 0.0,
"delay_ps": 786.57,
"vias_per_signal": 2
},
"R21": {
"n": "PERn9",
"p": "PERp9",
"len_n_mm": 118.082,
"len_p_mm": 118.082,
"intra_pair_skew_mm": 0.0,
"delay_ps": 810.26,
"vias_per_signal": 2
},
"P22": {
"n": "PETn10",
"p": "PETp10",
"len_n_mm": 113.876,
"len_p_mm": 113.876,
"intra_pair_skew_mm": 0.0,
"delay_ps": 786.57,
"vias_per_signal": 2
},
"R22": {
"n": "PERn10",
"p": "PERp10",
"len_n_mm": 118.455,
"len_p_mm": 118.455,
"intra_pair_skew_mm": 0.0,
"delay_ps": 810.26,
"vias_per_signal": 2
},
"P23": {
"n": "PETn11",
"p": "PETp11",
"len_n_mm": 114.541,
"len_p_mm": 114.541,
"intra_pair_skew_mm": 0.0,
"delay_ps": 786.57,
"vias_per_signal": 2
},
"R23": {
"n": "PERn11",
"p": "PERp11",
"len_n_mm": 116.466,
"len_p_mm": 116.466,
"intra_pair_skew_mm": 0.0,
"delay_ps": 810.26,
"vias_per_signal": 3
},
"P30": {
"n": "PETn12",
"p": "PETp12",
"len_n_mm": 133.262,
"len_p_mm": 133.262,
"intra_pair_skew_mm": -0.0,
"delay_ps": 778.68,
"vias_per_signal": 0
},
"R30": {
"n": "PERn12",
"p": "PERp12",
"len_n_mm": 133.044,
"len_p_mm": 133.044,
"intra_pair_skew_mm": 0.0,
"delay_ps": 806.46,
"vias_per_signal": 3
},
"P31": {
"n": "PETn13",
"p": "PETp13",
"len_n_mm": 113.279,
"len_p_mm": 113.279,
"intra_pair_skew_mm": 0.0,
"delay_ps": 778.68,
"vias_per_signal": 2
},
"R31": {
"n": "PERn13",
"p": "PERp13",
"len_n_mm": 117.177,
"len_p_mm": 117.177,
"intra_pair_skew_mm": -0.0,
"delay_ps": 806.46,
"vias_per_signal": 2
},
"P32": {
"n": "PETn14",
"p": "PETp14",
"len_n_mm": 112.385,
"len_p_mm": 112.385,
"intra_pair_skew_mm": 0.0,
"delay_ps": 778.68,
"vias_per_signal": 2
},
"R32": {
"n": "PERn14",
"p": "PERp14",
"len_n_mm": 117.712,
"len_p_mm": 117.712,
"intra_pair_skew_mm": 0.0,
"delay_ps": 806.45,
"vias_per_signal": 2
},
"P33": {
"n": "PETn15",
"p": "PETp15",
"len_n_mm": 113.331,
"len_p_mm": 113.331,
"intra_pair_skew_mm": 0.0,
"delay_ps": 778.68,
"vias_per_signal": 2
},
"R33": {
"n": "PERn15",
"p": "PERp15",
"len_n_mm": 115.673,
"len_p_mm": 115.673,
"intra_pair_skew_mm": 0.0,
"delay_ps": 806.45,
"vias_per_signal": 3
},
"CLK0": {
"n": "REFCLKn0",
"p": "REFCLKp0",
"len_n_mm": 121.267,
"len_p_mm": 121.267,
"intra_pair_skew_mm": 0.0,
"delay_ps": 829.63,
"vias_per_signal": 2
},
"CLK1": {
"n": "REFCLKn1",
"p": "REFCLKp1",
"len_n_mm": 132.008,
"len_p_mm": 132.025,
"intra_pair_skew_mm": -0.0166,
"delay_ps": 905.08,
"vias_per_signal": 3
},
"CLK2": {
"n": "REFCLKn2",
"p": "REFCLKp2",
"len_n_mm": 148.233,
"len_p_mm": 148.25,
"intra_pair_skew_mm": -0.0166,
"delay_ps": 1047.78,
"vias_per_signal": 5
},
"CLK3": {
"n": "REFCLKn3",
"p": "REFCLKp3",
"len_n_mm": 161.15,
"len_p_mm": 161.166,
"intra_pair_skew_mm": -0.0166,
"delay_ps": 1138.34,
"vias_per_signal": 7
}
},
"bifurcation": {
"PRSNTB[3:0]#": "0b0011",
"meaning": "SFF 4C+ '4 x4' card: 4x4, 4x2, 4x1 (OCP NIC 3.0 v1.6.0 Table 45); with a 1-socket host (BIF 0b000) the link is 4 x4",
"straps": "PRSNTB3# (B70) and PRSNTB2# (A12) to PRSNTA0# (A10) through 100 ohm (spec 0-200 ohm); PRSNTB1#/PRSNTB0# open",
"scan_chain_byte0": "A,B (PRSNTB0#,PRSNTB1#)=1, C,D=0, E=WAKE0#, F,G (TEMP_WARN_N, TEMP_CRIT_N)=1, H (FAN_ON_AUX)=0"
},
"refclk_perst": "port k = lanes 4k..4k+3 with REFCLKk and PERSTk# (OCP Table 47); REFCLK passed through (100 MHz HCSL, 85 ohm), PERST# buffered by SN74LVC125A with 33 ohm series and 100k pull-down",
"nic_pwr_good": {
"part": "TPS3808G33",
"threshold_V": 3.07,
"delay_ms_CT_open": 20,
"TAPL_max_ms": 50,
"TAUX_ID_max_ms": 10,
"note": "MR# = AUX_PWR_EN0: PWR_GOOD drops immediately when AUX_PWR_EN falls; ID and programming modes keep it low"
},
"power_budget": {
"+3V3_EDGE_mA_worst": 10,
"+3V3_limit_A": 1.1,
"+12V_EDGE_mA": 2.1,
"+12V_limit_A": 6.6,
"card_max_W": 0.1
},
"ac_coupling": "none: host TX caps are on the baseboard (OCP 4.5.1.2), device TX caps on the device; a passive riser must not add a second set",
"via_counts": "lane 0 TX 0 vias, lane 0 RX 3, lanes 1-2 2 each, lane 3 TX 2 / RX 3 (one layer drop for the lane reversal); via-in-pad at the OCuLink pads (JLC 6L filled and capped)"
}