Build clips

The whole build, filmed off the screen while Claude worked in Adom Hydrogen, cut to 16x speed with a voice-over for each part. New clips land here as the build goes on.

The video (3 min 3 s)

What the card is for (the server, the AIOM slot, the drives and GPU docks it opens up), then the whole build: the spec research, the 85 ohm pairs and length tuning, the board landing live in KiCad, the field-solved current check, the export and the finish line. Captions on (press C) and chapters on the timeline. Download the video.

Product photos: Supermicro, ServeTheHome, Delock, ChargerLAB (credited in the video).

Clip	Real time	What happens
1. The request and the research	0:00 to 0:46	The prompt, the OCP 3.0 and OCuLink specs, the aiflow timeline, the 85 ohm field solver
2. Routing the high-speed lanes	0:52 to 1:38	The netlist, 36 differential pairs routed and length-tuned, the slow-net router, the connector model
3. Design rule check and the design record	1:38 to 2:25	KiCad DRC, fixes at the source, a pause to ask before taking over the screen, skew results
4. Scan chain, parts and sourcing	2:25 to 3:12	The router converging, the outline fix, the OCP scan chain, new component pages, live stock
5. Design rules and routing closed	3:12 to 3:59	Steps declared on the timeline, JLCPCB 6-layer rules, every net routed, final DRC and cleanup
6. The board opens in KiCad	3:59 to 4:45	Last routing fixes, the real board in KiCad, parts staged for placement
7. Placement and the routing gate	4:46 to 5:33	47 parts landed live one at a time, the routing gate, tracks landing
8. Routing lands live	5:33 to 6:19	169 traces landed one at a time in KiCad, all accepted
9. Pours, outline and the current check	6:20 to 7:06	Routing done, pours landed and measured, the field-solved current check
10. Debugging the field solver	7:06 to 7:53	The board waits in KiCad while Claude finds why the current solve will not converge
11. The via ring, a finer solve, and silkscreen	7:59 to 8:45	Why the current solve failed, the 0.1 mm re-solve, silkscreen layout on both faces
12. Current, thermal, net tour, silkscreen and 3D	8:40 to 9:26	The current and thermal checks pass, the pour walkthrough, clean silkscreen, the 3D board
13. Analysis drawings, export and the finish line	9:32 to 10:17	Heat and current maps, Gerbers/BOM/CPL exported and checked, renders, the finish step
14. Clean DRC and the final re-solve	10:18 to 11:04	Zero DRC errors, a last test-point move, every result re-measured on the final board
15. The finish line	11:05 to 11:51	Finish passes, all 19 steps done, Gerbers/BOM/CPL exported, the 3D model for the page

1. The request and the research

Download clip 1 (2 min 53 s, 16x, narrated)

• The request is a YouTube comment: an OCuLink riser for the AIOM port on a Supermicro server.
• The AIOM slot is Supermicro's OCP NIC 3.0 small form factor slot. Claude reads the OCP 3.0 spec and the OCuLink connector standards, including the pinout tables in the PDFs.
• It finds the Amphenol OCuLink receptacle drawing and the 168-pin edge layout, including the present and bifurcation pins that tell the server how to split the x16 link.
• The adom-aiflow timeline opens: the clock starts at the prompt, and every gate from design rules to Gerbers is listed.
• It writes a small 2D field solver for 85 ohm differential pairs on a 6-layer stackup, then checks the card outline and keep-out zones against the spec drawings.

2. Routing the high-speed lanes

Download clip 2 (2 min 53 s, 16x, narrated)

• The design becomes data first: 51 components, 109 nets and 418 connected pins in a netlist.
• Claude routes the 36 high-speed differential pairs with its own router, from the gold fingers to the OCuLink connectors with no crossings.
• Accordion bumps tune each lane's length so the lanes in a port match to within 0.01 ps.
• Its clearance check finds two near misses between a reference clock pair and a transmit lane; it moves a via and re-checks until they are gone.
• A multi-layer maze router takes the slow nets (power, ground, resets, the scan chain) in the background.
• It writes the KiCad 10 schematic generator and models the OCuLink receptacle from the Amphenol drawing, labelled as AI-generated, since no vendor 3D model exists.

3. Design rule check and the design record

Download clip 3 (2 min 53 s, 16x, narrated)

• Every slow net routes with zero failures; the grounds are fanned out, the planes stitched, and KiCad's own DRC runs on the result.
• The first DRC finds clearances, duplicate vias, a short near the ESD parts and courtyard overlaps; each is fixed in the generator, not patched on the board.
• The run pauses on a question: the next stages draw the copper live in KiCad on this computer and film it, so Claude asks first. The answer (go ahead, on this box, now) comes about 15 minutes later.
• Local routing for the ESD grounds, and via placement that keeps a safe hole-to-hole distance from every plated hole.
• The design record: impedance per layer, delay matching per port, the present-pin encoding and the power-good timing. Skew inside each pair is at most 0.017 mm against the spec's 0.127 mm.

4. Scan chain, parts and sourcing

Download clip 4 (2 min 53 s, 16x, narrated)

• The rip-up router converges, one stuck net fewer each round.
• The DRC list narrows to recurring issues; a malformed outline (tiny arc stubs at the corners) is fixed in the outline generator and the pipeline re-runs.
• The SN74LV165A shift register is the card's OCP 3.0 scan chain: it reports the card's status and details to the server, alongside the present pins that signal a card is installed.
• Two parts get new Adom wiki component pages, including the OCuLink receptacle, with a provenance record marking which files are AI-generated.
• Live Mouser and DigiKey stock checks for the new capacitor and the status LED, and a bill of materials of orderable parts.

5. Design rules and routing closed

Download clip 5 (2 min 53 s, 16x, narrated)

• One follow-up prompt here: declare each adom-aiflow step as you go. The timeline moves to step 2, design rules.
• JLCPCB 6-layer rules: 0.09 mm trace and space, 0.15 mm drill, 0.2 mm edge clearance, plus an exception for the OCuLink connector's alignment pegs from Amphenol's land pattern.
• The router closes: every low-speed net connected, ground vias fanned out, final board build and DRC.
• A second note: update adom-aiflow, whose latest version covers high-speed boards where the AI brings its own router into the flow.
• The final check finds dangling copper stubs and a bug in the cleanup step that deleted a whole diagonal segment instead of trimming it; Claude fixes the pruning and rebuilds.

6. The board opens in KiCad

Download clip 6 (2 min 53 s, 16x, narrated)

• Last fixes to the routing script: a wake signal is re-routed on its own layers so it never crosses the high-speed lanes.
• KiCad opens with the real board: gold fingers along the bottom edge, the OCuLink connectors along the top, length-tuned pairs between them through the copper pours.
• The small parts are staged beside the board: the scan chain chip, its resistors, the status LED and the decoupling capacitors.
• The components and libraries steps check that every part has a footprint and a 3D model before placement.

7. Placement and the routing gate

Download clip 7 (2 min 53 s, 16x, narrated)

• Routing sends the run back to placement for a rework; the small parts return to the staging area beside the board.
• adom-aiflow lands the parts live, one at a time, each its own undo step: 47 parts in about 90 seconds.
• The routing plan goes through the gate before any copper lands. The first try finds 39 unconnected pins; after a fix it passes with zero new DRC errors and zero unconnected.
• The tracks then land live one at a time, each checked against the design rules before it goes down.

8. Routing lands live

Download clip 8 (2 min 53 s, 16x, narrated)

• With the plan through its gate at zero errors, every trace goes onto the real board in KiCad as its own undo step.
• The low-speed nets fill in on the left of the board: scan chain, resets, power-good and the LED. The high-speed lanes were already in place.
• Each trace is checked against the design rules before it lands.
• 169 traces land, every one accepted, in about 70 minutes of real time.

9. Pours, outline and the current check

Download clip 9 (2 min 53 s, 16x, narrated)

• The last traces land; every net is connected on the real board. The design calculations (impedance, skew, timing) go into the run as evidence.
• Heatsink vias: none needed, nothing on this passive card dissipates real power. The pours land and the filled copper is measured on all six layers.
• The outline corners were already rounded by the generator.
• The current check needs a real field solve of the board's copper, so adom-fields runs on the saved board. Early answers are refused (a stale report, current injected at every pad) until the spec carries the real +12 V path from the edge fingers to the loads.

10. Debugging the field solver

Download clip 10 (2 min 53 s, 16x, narrated)

• The board stays on screen in KiCad; the work is in the chat behind it.
• The field solver will not converge on the +3.3 V net, so Claude instruments the solver's own source: it drops floating copper islands from the DC solve and checks for current injected into unconnected cells.
• From clip 11 on, the chat window is filmed as well.

11. The via ring, a finer solve, and silkscreen

Download clip 11 (2 min 53 s, 16x, narrated, filmed from the chat window)

• The cause: the vias leave a 0.1 mm copper ring, which vanishes at the solver's default grid and splits the +3.3 V net in two.
• The full solve re-runs at a 0.1 mm grid; meanwhile Claude works ahead.
• Silkscreen to JLCPCB's rules (0.8 mm minimum text height), with reference labels and port legends on both faces, sized from measured text extents.
• Silkscreen renders of both faces: a description of the card on the bottom, a label on each OCuLink port on top.

12. Current, thermal, net tour, silkscreen and 3D

Download clip 12 (2 min 53 s, 16x, narrated)

• The fine solve finishes and the current check passes (field solve and IPC width check agree); the thermal check passes right after.
• The field tour covers every loaded net and part: zero issues.
• The pour walkthrough in KiCad lights each poured net on its own.
• Silkscreen: zero coverage errors, zero missing obstacles, zero collisions.
• The board in KiCad's 3D viewer, with the OCuLink connectors, gold fingers and labelled test points.

13. Analysis drawings, export and the finish line

Download clip 13 (2 min 53 s, 16x, narrated, filmed from the chat window)

• The analysis drawings: current density, heat flow per layer and temperature rise. About 0.1 A on the card; peak rise 0.066 C.
• The export: Gerbers for all six copper layers plus silkscreen, mask, paste and edge cuts, drill files, pick-and-place and BOM, each read back and checked against the board.
• Export check: 6 copper layers, 820 plated holes, 8 unplated holes (the OCuLink alignment pegs), CPL and BOM matching all 38 placed parts.
• Renders of the finished card for the project page, then the timeline reaches step 18, the finish line.

14. Clean DRC and the final re-solve

Download clip 14 (2 min 53 s, 16x, narrated, filmed from the chat window)

• KiCad's DRC on the live board: zero errors, zero unconnected.
• Test point 1 moves off a busy scan chain clock trace; every affected check runs again.
• Results are tied to the exact board they measured, so the final board is solved again and the 3D images re-rendered.
• Same answer on the final board: 47 A/mm2 peak on the narrowest copper, residuals under 1e-7. Then both analyses and finish run on it.

15. The finish line

Download clip 15 (2 min 53 s, 16x, narrated, filmed from the chat window)

• Current and thermal pass again on the final board; finish runs KiCad's full DRC once more and passes.
• All 19 steps are ticked: finished, Gerbers, BOM and CPL exported.
• The board becomes a 3D model for the wiki viewer, axis fixed so it lies flat, pads copper where the fab leaves them exposed.