OCuLink Riser for the Supermicro AIOM Slot

{
 "video": "/john/oculink-aiom-riser/render/clips/highlight.mp4",
 "poster": "/john/oculink-aiom-riser/render/clips/highlight-poster.jpg",
 "chapters": [
  {
   "t": 0,
   "title": "The request"
  },
  {
   "t": 20,
   "title": "What this board does"
  },
  {
   "t": 108.97,
   "title": "Spec research and impedance"
  },
  {
   "t": 148.97,
   "title": "Routing the high-speed lanes"
  },
  {
   "t": 220.97,
   "title": "The board in KiCad"
  },
  {
   "t": 278.97,
   "title": "Current and thermal checks"
  },
  {
   "t": 313.97,
   "title": "Silkscreen and 3D"
  },
  {
   "t": 331.97,
   "title": "Export and the finish line"
  }
 ],
 "captions": "WEBVTT\n\n00:00:00.400 --> 00:00:05.096\nA YouTube viewer asked for an OCuLink\nriser for the AIOM slot on their\n\n00:00:05.096 --> 00:00:06.304\nSupermicro server.\n\n00:00:06.304 --> 00:00:09.256\nBefore we build it, here is what that\nmeans.\n\n00:00:20.500 --> 00:00:23.854\nThis is the kind of server the viewer has:\n\n00:00:23.854 --> 00:00:25.850\na Supermicro rack server.\n\n00:00:25.850 --> 00:00:32.318\nInside, besides the normal P C I e slots,\nnewer Supermicro boards have one or two\n\n00:00:32.318 --> 00:00:33.196\nAIOM slots.\n\n00:00:34.600 --> 00:00:37.976\nFrom the back, Supermicro labels them:\n\n00:00:37.976 --> 00:00:40.997\nP C I e by sixteen, AIOM, OCP 3.0.\n\n00:00:40.997 --> 00:00:47.128\nA full sixteen lane slot, the same\nbandwidth as a graphics card slot.\n\n00:00:48.520 --> 00:00:50.584\nBut only one kind of card fits:\n\n00:00:50.584 --> 00:00:52.914\nan AIOM network card like this one.\n\n00:00:52.914 --> 00:00:57.640\nIf you don't need another network card,\nthose sixteen lanes sit unused.\n\n00:00:59.040 --> 00:01:00.799\nThis board changes that.\n\n00:01:00.799 --> 00:01:06.662\nIt plugs into the AIOM slot in place of\nthe network card, and splits the sixteen\n\n00:01:06.662 --> 00:01:11.352\nlanes into four OCuLink ports, each a full\nP C I e by four link.\n\n00:01:12.760 --> 00:01:18.420\nRun an OCuLink cable from each port to a U\ndot two NVMe drive, and the server gains\n\n00:01:18.420 --> 00:01:23.808\nfour more fast drives, each running at\nfull Gen four by four speed, about eight\n\n00:01:23.808 --> 00:01:25.240\ngigabytes per second.\n\n00:01:26.640 --> 00:01:31.888\nOr cable a port to an OCuLink dock like\nthis one, and hang a graphics card or\n\n00:01:31.888 --> 00:01:35.568\nanother P C I e card off the server,\noutside the case.\n\n00:01:36.960 --> 00:01:38.269\nThere is one catch:\n\n00:01:38.269 --> 00:01:42.607\nthe server's BIOS has to support splitting\nthat slot four ways.\n\n00:01:42.607 --> 00:01:47.635\nWhen it does, an unused network slot\nbecomes four general purpose P C I e\n\n00:01:47.635 --> 00:01:48.048\nports.\n\n00:01:49.370 --> 00:01:50.427\nNow the build.\n\n00:01:50.427 --> 00:01:54.653\nWe typed that one request into Claude, in\nAdom Hydrogen.\n\n00:01:54.653 --> 00:02:00.314\nIt reads the OCP 3.0 spec and the OCuLink\nstandards, pinout tables and all.\n\n00:02:09.370 --> 00:02:14.713\nIt writes a small field solver and finds\ntrace widths for 85 ohm differential pairs\n\n00:02:14.713 --> 00:02:16.258\non a six layer stack-up.\n\n00:02:29.370 --> 00:02:34.171\nThirty six high speed pairs are routed\nfrom the gold fingers to four OCuLink\n\n00:02:34.171 --> 00:02:36.066\nconnectors, with no crossings.\n\n00:02:49.370 --> 00:02:54.283\nEvery lane in a port is tuned to arrive\nwithin a hundredth of a picosecond of its\n\n00:02:54.283 --> 00:02:54.890\nneighbors.\n\n00:03:04.370 --> 00:03:05.548\nThe design record:\n\n00:03:05.548 --> 00:03:10.850\nimpedance per layer, skew inside every\npair under two hundredths of a millimeter.\n\n00:03:24.370 --> 00:03:29.822\nOn the adom-aiflow timeline, the run moves\nthrough design rules:\n\n00:03:29.822 --> 00:03:32.122\nJLCPCB's six layer process.\n\n00:03:41.370 --> 00:03:43.801\nThen the real board opens in KiCad:\n\n00:03:43.801 --> 00:03:47.274\ngold fingers at the bottom, connectors at\nthe top.\n\n00:03:59.370 --> 00:04:04.818\nForty seven parts land live, one at a\ntime, each its own undo step.\n\n00:04:19.370 --> 00:04:24.268\nThen one hundred sixty nine traces land\nthe same way, every one checked against\n\n00:04:24.268 --> 00:04:25.322\nthe design rules.\n\n00:04:39.370 --> 00:04:42.141\nThe current check needs a real field\nsolve.\n\n00:04:42.141 --> 00:04:43.816\nClaude finds why it fails:\n\n00:04:43.816 --> 00:04:47.554\na tenth of a millimeter via ring the\nsolver could not see.\n\n00:04:59.370 --> 00:05:02.970\nWith a finer grid, current and thermal\nboth pass.\n\n00:05:14.370 --> 00:05:18.617\nClean silkscreen, and the finished board\nin KiCad's 3D viewer:\n\n00:05:18.617 --> 00:05:20.946\nevery test point and port labeled.\n\n00:05:32.370 --> 00:05:37.329\nGerbers for all six copper layers, drill\nfiles, pick and place and the bill of\n\n00:05:37.329 --> 00:05:40.890\nmaterials, each read back and checked\nagainst the board.\n\n00:05:57.370 --> 00:05:58.413\nFinish passes:\n\n00:05:58.413 --> 00:06:01.543\nzero design rule errors, zero unconnected.\n\n00:06:01.543 --> 00:06:07.280\nA manufacturable PCI Express Gen four\ncard, from a one line comment, designed\n\n00:06:07.280 --> 00:06:10.186\nand checked by Claude in Adom Hydrogen.\n\n"
}