NTX_CCX-MIO_Carrier_v1.1/
  NTX_CCX-MIO_Carrier_v1.1.kicad_pro    # Project file
  NTX_CCX-MIO_Carrier_v1.1.kicad_sch    # Schematic
  NTX_CCX-MIO_Carrier_v1.1.kicad_pcb    # PCB layout (routed)
  jlcpcb/production_files/               # BOM, CPL, gerbers
  DRC.rpt                                # DRC report

# NTX CCX-MIO Carrier v1.1

## Project Overview

| Field          | Value                          |
|----------------|--------------------------------|
| Project Name   | NTX_CCX-MIO_Carrier_v1.1       |
| KiCad Version  | 9.0                            |
| Board          | 192 × 160 mm, 2-layer          |
| Schematic      | Single-page (no sub-sheets)    |
| PCB Layout     | Complete — fabbed (JLCPCB gerbers in bundle) |
| DRC            | 0 violations (2026-07-15 run; 9 unconnected pads noted — see [DRC report](DRC_Report.rpt)) |

The NTX CCX-MIO Carrier is a passive carrier/interconnect board routing signals between 17 external connectors and 78 machine contacts (plus 4 machine pins). It contains no active components, power regulation, or complex circuitry — it functions purely as a mechanical and electrical interface adapter for the NTX Embedded Octolux IO board.

## v1.1 Changes

1. Silkscreen updated to reflect the physical board
2. Fill zone updated to remove conflict

(see [Rev Notes](Rev_Notes.txt))

## Component Summary

| Type               | Ref Designators | Count |
|--------------------|-----------------|-------|
| Connectors         | J1 – J19 (gaps: J12, J14) | 17 |
| Machine Contacts   | MC1 – …         | 78    |
| Machine Pins       | MP1 – MP4       | 4     |
| **Total**          |                 | **99** |

## Connectors (as routed, v1.1)

| Reference | Footprint | Pins |
|-----------|-----------|------|
| J1  | PinSocket_1x04_P2.54mm_Vertical | 4 |
| J2  | PinSocket_1x04_P2.54mm_Vertical | 4 |
| J3  | PinSocket_2x04_P2.54mm_Vertical | 8 |
| J4  | PinHeader_2x02_P2.54mm_Vertical | 4 |
| J5  | PinHeader_2x05_P2.54mm_Vertical | 10 |
| J6  | PinHeader_2x02_P2.54mm_Vertical | 4 |
| J7  | PinHeader_2x05_P2.54mm_Vertical | 10 |
| J8  | PinHeader_1x02_P2.54mm_Vertical | 2 |
| J9  | PinSocket_1x03_P2.54mm_Vertical | 3 |
| J10 | PinSocket_2x05_P2.00mm_Vertical | 10 |
| J11 | PinSocket_2x04_P2.00mm_Vertical | 8 |
| J13 | PinSocket_1x03_P2.54mm_Vertical | 3 |
| J15 | PinHeader_1x06_P2.54mm_Vertical | 6 |
| J16 | PinSocket_1x04_P2.54mm_Vertical | 4 |
| J17 | PinHeader_1x02_P2.54mm_Vertical | 2 |
| J18 | PinHeader_1x05_P2.54mm_Vertical | 5 |
| J19 | PinHeader_1x02_P2.54mm_Vertical | 2 |

## Machine Interface Components

- **Machine Contacts (×78)**: `adom-kicad-footprint-library:MachineContact` — `MachineContactMedium` footprint
- **Machine Pins (MP1–MP4)**: `adom-kicad-footprint-library:MachinePin` — `MachinePinMediumShort` footprint

## Net Labels / Signal Mapping

Copy-paste-ready labels are in [net_labels.txt](net_labels.txt). *Note: the label set was captured at the v1.0 schematic stage (22 connectors); the routed v1.1 board carries 17 connectors — treat labels for removed connectors as historical.*

## Design Settings

| Parameter              | Value   |
|------------------------|---------|
| Default Track Width    | 0.2 mm  |
| Default Clearance      | 0.2 mm  |
| Via Diameter           | 0.6 mm  |
| Via Drill              | 0.3 mm  |
| Diff Pair Width        | 0.2 mm  |
| Diff Pair Gap          | 0.25 mm |
| Microvia Diameter      | 0.3 mm  |
| Microvia Drill         | 0.1 mm  |

## Custom Libraries

- **adom-kicad-footprint-library** — provides `MachineContact`, `MachinePin`, `MachineContactMedium`, and `MachinePinMediumShort` symbols and footprints

## File Structure

```
NTX_CCX-MIO_Carrier_v1.1/
  NTX_CCX-MIO_Carrier_v1.1.kicad_pro    # Project file
  NTX_CCX-MIO_Carrier_v1.1.kicad_sch    # Schematic
  NTX_CCX-MIO_Carrier_v1.1.kicad_pcb    # PCB layout (routed)
  jlcpcb/production_files/               # BOM, CPL, gerbers
  DRC.rpt                                # DRC report
```