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Name	Last commit message	Last updated
docs	overview updated to v1.1 as-routed reality; net_labels for link integrity	5d ago
screenshots	dimmed hero lighting	4d ago
BOM-NTX_CCX-MIO_Carrier_v1.1.csv	Publish 1.1.0	11d ago
CPL-NTX_CCX-MIO_Carrier_v1.1.csv	Publish 1.1.0	11d ago
GERBER-NTX_CCX-MIO_Carrier_v1.1.zip	Publish 1.1.0	11d ago
NTX_CCX-MIO_Carrier_v1.1_footprint.json	Publish 1.1.0	11d ago
NTX_CCX-MIO_Carrier_v1.1_symbol.json	Publish 1.1.0	11d ago
NTX_CCX-MIO_Carrier_v1.1.glb	Publish 1.1.0	11d ago
NTX_CCX-MIO_Carrier_v1.1.kicad_pcb	Publish 1.1.0	11d ago
NTX_CCX-MIO_Carrier_v1.1.kicad_pro	Publish 1.1.2	11d ago
NTX_CCX-MIO_Carrier_v1.1.kicad_sch	Publish 1.1.0	11d ago
NTX_CCX-MIO_Carrier_v1.1.step	Publish 1.1.0	11d ago
package.json	Publish 1.1.4	10d ago
page.json	Set hero: screenshots/hero.png	5d ago
README.md	add project overview, v1.1 rev notes, fresh DRC report	5d ago

NTX_CCX-MIO_Carrier_v1.1

NTX CCX-MIO carrier molecule, exported from KiCad and converted via the OCCT molecule pipeline (step2glb job ce596f6daa02aa6b, 2026-07-09).

Bundle

File	Role
`NTX_CCX-MIO_Carrier_v1.1.glb`	OCCT-generated model — anchored (FL marker MP2), gold-upgraded (125 surfaces), draco-compressed
`NTX_CCX-MIO_Carrier_v1.1.step`	Source 3D export from the design machine (machine pins/contacts/markers baked in)
`NTX_CCX-MIO_Carrier_v1.1.kicad_pcb` / `.kicad_sch`	Board + schematic sources
`NTX_CCX-MIO_Carrier_v1.1_footprint.json`	Per-pad wire-attach heights (contact_z 5.6 mm), 4 machine pins + 117 contacts
`NTX_CCX-MIO_Carrier_v1.1_symbol.json`	Generated symbol metadata
`GERBER-.zip`, `BOM-.csv`, `CPL-*.csv`	JLCPCB production extras

Conversion stats (gates passed)

molecule_anchored: true, up-axis Z, origin_z −0.0066
footprint_applied: true, pin size medium (78× MachineContactMedium)
contact_z: 5.6 mm, warnings: []

Import

adom-molecule import ntx-ccx-mio-carrier --owner <you>

Reuses this GLB (--no-optimize) — do not regenerate from the EDA export.

Pin Map

J1 — RS485 (mates: 705530003)

Pin	Net
1	`J1_+5V`
2	`J1_RS485-B`
3	`J1_RS485-A`
4	`J1_GND`

J2 — RS485 (mates: 705530003)

Pin	Net
1	`J2_+5V`
2	`J2_RS485-B`
3	`J2_RS485-A`
4	`J2_GND`

J3 — ANALOGUE OUT 0-10V (mates: 0901303108)

Pin	Net
1	`J3_0-10V_CH1`
2	`J3_GND`
3	`J3_0-10V_CH2`
4	`J3_GND`
5	`J3_0-10V_CH3`
6	`J3_GND`
7	`J3_0-10V_CH4`
8	`J3_GND`

J4 — DIG OUT 1 PWR SEL

Pin	Net
1	`J4_12-24_VIN`
2	`J4_U7_COM`
3	`J4_FIL_VBUS`
4	`J4_U7_COM`

J5 — DIGITAL OUT 1 (mates: 0741640110)

Pin	Net
1	`J5_U7_COM`
2	`J5_GND`
3	`J5_D6_OUT`
4	`J5_D7_OUT`
5	`J5_D4_OUT`
6	`J5_D5_OUT`
7	`J5_D2_OUT`
8	`J5_D3_OUT`
9	`J5_D0_OUT`
10	`J5_D1_OUT`

J6 — DIG OUT 2 PWR SEL

Pin	Net
1	`J6_12-24_VIN`
2	`J6_U8_COM`
3	`J6_FIL_VBUS`
4	`J6_U8_COM`

J7 — DIGITAL OUT 2 (mates: 0741640110)

Pin	Net
1	`J7_U8_COM`
2	`J7_GND`
3	`J7_D14_OUT`
4	`J7_D15_OUT`
5	`J7_D12_OUT`
6	`J7_D13_OUT`
7	`J7_D10_OUT`
8	`J7_D11_OUT`
9	`J7_D8_OUT`
10	`J7_D9_OUT`

J8 — PWM OUT (mates: 0705530001)

Pin	Net
1	`J8_OUT`
2	`J8_GND`

J9 — DIG-IN PULL

Pin	Net
1	`J9_GND`
2	`J9_D-IN_GATE_PULL`
3	`J9_HIGH_JMP5`

J10 — DIGITAL-IN (mates: 0878331032)

Pin	Net
1	`J10_GATE_+D-IN0`
2	`J10_GATE_+D-IN1`
3	`J10_GATE_+D-IN2`
4	`J10_GATE_+D-IN3`
5	`J10_GATE_+D-IN4`
6	`J10_GATE_+D-IN5`
7	`J10_GATE_+D-IN6`
8	`J10_GATE_+D-IN7`
9	`J10_HIGH`
10	`J10_GND`

J11 — CURRENT OUT 0-20mA (mates: 0878330832)

Pin	Net
1	`J11_OUT0`
2	`J11_GND`
3	`J11_OUT1`
4	`J11_GND`
5	`J11_OUT2`
6	`J11_GND`
7	`J11_OUT3`
8	`J11_GND`

J13 — EXT PWR +12V TO +24V (mates: 2-1445098-3)

Pin	Net
1	`J13_GND`
2	`J13_12-24V`
3	`J13_CHASSIS`

J15 — AUX SPI

Pin	Net
1	`J15_3V3`
2	`J15_SPI2_SCK`
3	`J15_SPI2_MOSI`
4	`J15_SPI2_MISO`
5	`J15_SPI2_NSS`
6	`J15_GND`

J16 — AUX I2C

Pin	Net
1	`J16_3V3`
2	`J16_SCL`
3	`J16_SDA`
4	`J16_GND`

J17 — BOOT

Pin	Net
1	`J17_3V3`
2	`J17_BOOT0`

J18 — SWD

Pin	Net
1	`J18_VCC`
2	`J18_SWCLK_UART2_TX`
3	`J18_SWDIO_UART2_RX`
4	`J18_NRST`
5	`J18_GND`

J19 — NRST

Pin	Net
1	`J19_NRST`
2	`J19_GND`

JMP1 — RS485-JMP

Pin	Net
1	`JMP1_3V3`
2	`JMP1_RS485A`
3	`JMP1_120R`
4	`JMP1_RS485A`
5	`JMP1_120R`
6	`JMP1_RS485B`
7	`JMP1_GND`
8	`JMP1_RS485B`

JMP2 — MOD MASK

Pin	Net
1	`JMP2_PC10`
2	`JMP2_GND`
3	`JMP2_PC11`
4	`JMP2_GND`
5	`JMP2_PC12`
6	`JMP2_GND`
7	`JMP2_PC13`
8	`JMP2_GND`

JMP4 — MOD MASK

Pin	Net
1	`JMP4_GND`
2	`JMP4_PC6`
3	`JMP4_GND`
4	`JMP4_PC7`
5	`JMP4_GND`
6	`JMP4_PD8`
7	`JMP4_GND`
8	`JMP4_PD9`

JMP5 — DIGITAL LOGIC

Pin	Net
1	`JMP5_12-24V`
2	`JMP5_PULL`
3	`JMP5_FIL_VBUS`
4	`JMP5_PULL`
5	`JMP5_3V3`
6	`JMP5_PULL`

Machine contacts (MC1–MC78)

MC	Net	MC	Net
MC1	`J7_D8_OUT`	MC2	`J7_D10_OUT`
MC3	`J7_D12_OUT`	MC4	`J7_D14_OUT`
MC5	`J7_U8_COM`	MC6	`J3_0-10V_CH1`
MC7	`J3_0-10V_CH2`	MC8	`J3_0-10V_CH3`
MC9	`J3_0-10V_CH4`	MC10	`J5_D0_OUT`
MC11	`J5_D2_OUT`	MC12	`J5_D4_OUT`
MC13	`J5_D6_OUT`	MC14	`J5_U7_COM`
MC15	`J1_+5V`	MC16	`J1_RS485-B`
MC17	`J1_RS485-A`	MC18	`J1_GND`
MC19	`J2_+5V`	MC20	`J2_RS485-B`
MC21	`J2_RS485-A`	MC22	`J2_GND`
MC23	`J3_GND`	MC24	`J3_GND`
MC25	`J3_GND`	MC26	`J3_GND`
MC27	`J5_D1_OUT`	MC28	`J5_D3_OUT`
MC29	`J5_D5_OUT`	MC30	`J5_D7_OUT`
MC31	`J5_GND`	MC32	`J7_D9_OUT`
MC33	`J7_D11_OUT`	MC34	`J7_D13_OUT`
MC35	`J7_D15_OUT`	MC36	`J7_GND`
MC37	`J10_GATE_+D-IN0`	MC38	`J10_GATE_+D-IN2`
MC39	`J10_GATE_+D-IN4`	MC40	`J10_GATE_+D-IN6`
MC41	`J10_HIGH`	MC42	`J11_OUT0`
MC43	`J11_OUT1`	MC44	`J11_OUT2`
MC45	`J11_OUT3`	MC46	`J15_3V3`
MC47	`J15_SPI2_SCK`	MC48	`J8_OUT`
MC49	`J8_GND`	MC50	`J15_SPI2_MOSI`
MC51	`J15_SPI2_MISO`	MC52	`J13_GND`
MC53	`J13_12-24V`	MC54	`J13_CHASSIS`
MC55	`J15_SPI2_NSS`	MC56	`J15_GND`
MC57	`J10_GATE_+D-IN1`	MC58	`J10_GATE_+D-IN3`
MC59	`J10_GATE_+D-IN5`	MC60	`J10_GATE_+D-IN7`
MC61	`J10_GND`	MC62	`J11_GND`
MC63	`J11_GND`	MC64	`J11_GND`
MC65	`J11_GND`	MC66	`J17_3V3`
MC67	`J17_BOOT0`	MC68	`J16_3V3`
MC69	`J16_SCL`	MC70	`J16_SDA`
MC71	`J16_GND`	MC72	`J19_NRST`
MC73	`J19_GND`	MC74	`J18_VCC`
MC75	`J18_SWCLK_UART2_TX`	MC76	`J18_SWDIO_UART2_RX`
MC77	`J18_NRST`	MC78	`J18_GND`

Documents

Document	Purpose
Project Overview	Component summary, connectors, project facts
Rev Notes	v1.1 changes (silkscreen update, fill-zone fix)
DRC Report	2026-07-15 run — 0 violations, 9 unconnected pads noted