component
XL7026E1
Public Made by Adomby adom
XLSEMI DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
xl7026e1: backfill missing artifacts (etch, variants)
3 files changed
+22660−5
diff truncated
README.md+3−1@@ -29,7 +29,9 @@ XL7026E1 from XLSEMI, in a SOP-8-EP. Pinout and pin descriptions extracted from ## Ordering variants -- `XL7026E1E1`+Same part, different packaging or reel option.++- `XL7026E1` ## CAD (KiCad official)
page.json+11−4@@ -40,13 +40,13 @@ "number": "2", "name": "VREG", "type": "power_in",- "description": "Chip supply pin. Requires a 10 \u00b5F decoupling capacitor between VREG and GND to filter noise. An external 7-9 V bias can be applied to this pin to reduce internal power dissipation."+ "description": "Chip supply pin. Requires a 10 µF decoupling capacitor between VREG and GND to filter noise. An external 7-9 V bias can be applied to this pin to reduce internal power dissipation." }, { "number": "3", "name": "VC", "type": "passive",- "description": "Internal voltage-regulator bypass pin. Requires a 1 \u00b5F ceramic capacitor connected between VC and VIN."+ "description": "Internal voltage-regulator bypass pin. Requires a 1 µF ceramic capacitor connected between VC and VIN." }, { "number": "4",@@ -156,9 +156,16 @@ "docs/hero.png", "docs/xl7026e1-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "xl7026e1-etched.step" ], "visibility": { "public": true- }+ },+ "variants": [+ {+ "mpn": "XL7026E1",+ "kind": "packaging"+ }+ ] }
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