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docs xjng2102: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json xjng2102: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md xjng2102: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
xjng2102-etched.fit.json xjng2102: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
xjng2102-etched.glb xjng2102: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
xjng2102-etched.step xjng2102: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
xjng2102.glb Publish 0.1.0 · Ray
xjng2102.kicad_mod Publish 0.1.0 · Ray
xjng2102.kicad_sym Publish 0.1.0 · Ray
xjng2102.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
xjng2102.step Publish 0.1.0 · Ray

XJNG2102

Wuxi NCE Power Semiconductor · Isolators - Gate Drivers · SOIC-8

XJNG2102 from Wuxi NCE Power Semiconductor, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low side and main power supply. Recommended 6 V to 20 V (abs max 25 V) referenced to COM. Provides the low-side gate-drive rail and powers the internal logic.
2 HIN input Logic input for high-side gate driver output (HO). CMOS/LSTTL compatible down to 3.3 V logic; VIH >= 2.5 V, VIL <= 0.8 V. HO is in phase with HIN.
3 LIN input Logic input for low-side gate driver output (LO). CMOS/LSTTL compatible down to 3.3 V logic; VIH >= 2.5 V, VIL <= 0.8 V. LO is out of phase with LIN (inverting).
4 COM power_in Device ground / low-side return. All absolute voltage parameters are referenced to COM.
5 LO output Low-side gate drive output. Swings between COM and VCC with typical 1 A source / 1 A sink pulsed capability; drives the gate of the low-side N-channel power MOSFET.
6 VS power_in High-side floating supply return / bootstrap return. Connects to the source of the high-side MOSFET and the negative terminal of the bootstrap capacitor. Rated -6 V to +200 V (abs max VB-25 to VB+0.3), dV/dt tolerance up to 50 V/ns.
7 HO output High-side gate drive output, in phase with HIN. Swings between VS and VB with typical 1 A source / 1 A sink pulsed capability; drives the gate of the high-side N-channel power MOSFET.
8 VB power_in High-side floating supply (bootstrap supply positive rail). Recommended VS+6 V to VS+20 V (abs max 225 V to COM). Connects to the positive terminal of the bootstrap capacitor and cathode of the bootstrap diode.

Key specifications

Parameter Value
Manufacturer Wuxi NCE Power Semiconductor
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • XJNG2102

CAD (KiCad official)

  • Symbol: XJNG2102
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: xjng2102-etched.step / xjng2102-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xjng2102.step / xjng2102.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi NCE Power Semiconductor datasheet (6 pp, sha256 e3ae5b7b069d531a, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF