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XD74LS165

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XINLUDA Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD74LS165

XINLUDA · Registers · DIP-16

XD74LS165 from XINLUDA, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SH/LD input Shift/load input: while SH/LD is low, parallel data at A to H is loaded directly into the register independent of CLK, CLK INH, or SER, and parallel loading is inhibited while it is high (Req = 13 kΩ NOM).
2 CLK input Gated clock input: clocking is inhibited while held high, and with SH/LD high it is enabled when CLK INH is held low; the datasheet gives a clock frequency range of 0 to 25 MHz and a minimum clock-high pulse width of 15 ns.
3 E input Parallel data input for the fifth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum.
4 F input Parallel data input for the sixth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum.
5 G input Parallel data input for the seventh register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum.
6 H input Parallel data input for the eighth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum.
7 QH output Eighth-bit serial output of the register; the datasheet specifies IOL of 8 mA maximum and IOH of -0.4 mA, with VOH of 2.7 V minimum.
8 GND power_in Ground reference for the device (network ground terminal).
9 QH output Complementary output of the eighth bit (QH), provided alongside QH.
10 SER input Serial data input to the first register stage (QA), shifted toward QH on the clock; serial input setup time is 20 ns minimum.
11 A input Parallel data input for the first register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum.
12 B input Parallel data input for the second register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum.
13 C input Parallel data input for the third register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum.
14 D input Parallel data input for the fourth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum.
15 CLK INH input Clock inhibit input: holding it high inhibits clocking, and it should be changed to the high level only while CLK is high.
16 VCC power_in Supply voltage, 4.75 V minimum, 5 V nominal, 5.25 V maximum per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC 7 V see Note 1 4
Input voltage (74LS165) VI 7 V 74LS165 4
Interemitter voltage 5.5 V see Note 2 4
Package thermal impedance, N package θJA 67 °C/W N package, see Note 3 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VCC 4.75 5 5.25 V 74LS165 5
High-level input voltage VIH 2 V 5
Low-level input voltage VIL 0.8 V 5
High-level output current IOH -0.4 mA 5
Low-level output current IOL 8 mA 5
Clock frequency fclock 0 25 MHz 5
Width of clock input pulse, clock high tw(clock) 15 ns clock high 5
Width of clock input pulse, clock low tw(clock) 25 ns clock low 5
Width of load input pulse, clock high tw(load) 25 ns clock high 5
Width of load input pulse, clock low tw(load) 17 ns clock low 5
Clock-enable setup time tsu 30 ns 5
Parallel input setup time tsu 10 ns 5
Serial input setup time tsu 20 ns 5
Shift setup time tsu 45 ns 5
Hold time at any input th 0 ns 5
Operating free-air temperature TA 0 70 °C 5
High-level output voltage VOH 2.7 3.5 V VCC = MIN, VIH = 2 V, VIL = MAX, IOH = -0.4 mA 5
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, VIL = MAX, IOL = 4 mA 5
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, VIL = MAX, IOL = 8 mA 5
Input clamp voltage VIK -1.5 V VCC = MIN, II = -18 mA 5
Input current at maximum input voltage II 0.1 mA VCC = MAX, VI = 7 V 5
High-level input current IIH 20 µA VCC = MAX, VI = 2.7 V 5
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 5
Short-circuit output current IOS -20 -100 mA VCC = MAX 5
Supply current ICC 18 30 mA VCC = MAX 5
Maximum clock frequency fmax 25 35 MHz VCC = 5 V, TA = 25°C 6
Propagation delay, low-to-high-level output, LD to Any tPLH 21 35 ns RL =2k CL = 15 pF 6
Propagation delay, high-to-low-level output, LD to Any tPHL 26 35 ns RL = 2 k, CL = 15 pF 6
Propagation delay, low-to-high-level output, CLK to Any tPLH 14 25 ns RL =2k CL = 15 pF 6
Propagation delay, high-to-low-level output, CLK to Any tPHL 16 25 ns RL = 2 k, CL = 15 pF 6
Propagation delay, low-to-high-level output, H to QH (row 1) tPLH 13 25 ns RL =2k CL = 15 pF 6
Propagation delay, high-to-low-level output, H to QH (row 1) tPHL 24 30 ns RL = 2 k, CL = 15 pF 6
Propagation delay, low-to-high-level output, H to QH (row 2) tPLH 19 30 ns RL =2k CL = 15 pF 6
Propagation delay, high-to-low-level output, H to QH (row 2) tPHL 17 25 ns RL = 2 k, CL = 15 pF 6

CAD (KiCad official)

  • Symbol: XD74LS165
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: xd74ls165-etched.step / xd74ls165-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls165.step / xd74ls165.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (10 pp, sha256 0d0e0e24042cca96, retrieved 2026-10-25, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF