XD74LS165

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  "slug": "xd74ls165",
  "title": "XD74LS165",
  "brief": "XINLUDA Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
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  "component": {
    "mpn": "XD74LS165",
    "manufacturer": "XINLUDA",
    "package": "DIP-16",
    "pin_count": 16,
    "category": "Logic ICs",
    "subcategory": "Registers",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/eabd153fd377df654dd7c9acc6d0ff6e.pdf",
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    "distributor_links": {
      "lcsc": "C609767"
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    "distributor_check": {
      "checked_at": "2026-10-25T19:09:46Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
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      "mouser": {
        "pn": null,
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    },
    "pins": [
      {
        "number": "1",
        "name": "SH/LD",
        "type": "input",
        "description": "Shift/load input: while SH/LD is low, parallel data at A to H is loaded directly into the register independent of CLK, CLK INH, or SER, and parallel loading is inhibited while it is high (Req = 13 kΩ NOM)."
      },
      {
        "number": "2",
        "name": "CLK",
        "type": "input",
        "description": "Gated clock input: clocking is inhibited while held high, and with SH/LD high it is enabled when CLK INH is held low; the datasheet gives a clock frequency range of 0 to 25 MHz and a minimum clock-high pulse width of 15 ns."
      },
      {
        "number": "3",
        "name": "E",
        "type": "input",
        "description": "Parallel data input for the fifth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "4",
        "name": "F",
        "type": "input",
        "description": "Parallel data input for the sixth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "5",
        "name": "G",
        "type": "input",
        "description": "Parallel data input for the seventh register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "6",
        "name": "H",
        "type": "input",
        "description": "Parallel data input for the eighth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "output",
        "description": "Eighth-bit serial output of the register; the datasheet specifies IOL of 8 mA maximum and IOH of -0.4 mA, with VOH of 2.7 V minimum."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device (network ground terminal)."
      },
      {
        "number": "9",
        "name": "QH",
        "type": "output",
        "description": "Complementary output of the eighth bit (QH), provided alongside QH."
      },
      {
        "number": "10",
        "name": "SER",
        "type": "input",
        "description": "Serial data input to the first register stage (QA), shifted toward QH on the clock; serial input setup time is 20 ns minimum."
      },
      {
        "number": "11",
        "name": "A",
        "type": "input",
        "description": "Parallel data input for the first register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "12",
        "name": "B",
        "type": "input",
        "description": "Parallel data input for the second register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "13",
        "name": "C",
        "type": "input",
        "description": "Parallel data input for the third register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "14",
        "name": "D",
        "type": "input",
        "description": "Parallel data input for the fourth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "15",
        "name": "CLK INH",
        "type": "input",
        "description": "Clock inhibit input: holding it high inhibits clocking, and it should be changed to the high level only while CLK is high."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, 4.75 V minimum, 5 V nominal, 5.25 V maximum per the recommended operating conditions."
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