XD74LS165

{
  "slug": "xd74ls165",
  "version": "0.1.0",
  "type": "component",
  "description": "XINLUDA Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic ics",
    "xd74ls165",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "xd74ls165.kicad_sym",
    "xd74ls165.kicad_mod",
    "xd74ls165.glb",
    "xd74ls165.step",
    "xd74ls165.lbr",
    "docs/hero.png",
    "docs/xd74ls165-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "xd74ls165-hero.glb",
    "xd74ls165-hero.overlay.json",
    "xd74ls165-etched.glb"
  ],
  "component": {
    "mpn": "XD74LS165",
    "manufacturer": "XINLUDA",
    "package": "DIP-16",
    "pin_count": 16,
    "category": "Logic ICs",
    "subcategory": "Registers",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/eabd153fd377df654dd7c9acc6d0ff6e.pdf",
    "parts": {
      "symbol": "xd74ls165.kicad_sym",
      "footprint": "xd74ls165.kicad_mod",
      "model_3d": "xd74ls165-hero.glb",
      "model_3d_plain": "xd74ls165-etched.glb",
      "model_3d_step": "xd74ls165-etched.step",
      "model_3d_step_plain": "xd74ls165.step",
      "lbr": "xd74ls165.lbr"
    },
    "distributor_links": {
      "lcsc": "C609767"
    },
    "distributor_check": {
      "checked_at": "2026-10-25T19:09:46Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "SH/LD",
        "type": "input",
        "description": "Shift/load input: while SH/LD is low, parallel data at A to H is loaded directly into the register independent of CLK, CLK INH, or SER, and parallel loading is inhibited while it is high (Req = 13 kΩ NOM)."
      },
      {
        "number": "2",
        "name": "CLK",
        "type": "input",
        "description": "Gated clock input: clocking is inhibited while held high, and with SH/LD high it is enabled when CLK INH is held low; the datasheet gives a clock frequency range of 0 to 25 MHz and a minimum clock-high pulse width of 15 ns."
      },
      {
        "number": "3",
        "name": "E",
        "type": "input",
        "description": "Parallel data input for the fifth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "4",
        "name": "F",
        "type": "input",
        "description": "Parallel data input for the sixth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "5",
        "name": "G",
        "type": "input",
        "description": "Parallel data input for the seventh register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "6",
        "name": "H",
        "type": "input",
        "description": "Parallel data input for the eighth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "output",
        "description": "Eighth-bit serial output of the register; the datasheet specifies IOL of 8 mA maximum and IOH of -0.4 mA, with VOH of 2.7 V minimum."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device (network ground terminal)."
      },
      {
        "number": "9",
        "name": "QH",
        "type": "output",
        "description": "Complementary output of the eighth bit (QH), provided alongside QH."
      },
      {
        "number": "10",
        "name": "SER",
        "type": "input",
        "description": "Serial data input to the first register stage (QA), shifted toward QH on the clock; serial input setup time is 20 ns minimum."
      },
      {
        "number": "11",
        "name": "A",
        "type": "input",
        "description": "Parallel data input for the first register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "12",
        "name": "B",
        "type": "input",
        "description": "Parallel data input for the second register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "13",
        "name": "C",
        "type": "input",
        "description": "Parallel data input for the third register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "14",
        "name": "D",
        "type": "input",
        "description": "Parallel data input for the fourth register stage, loaded when SH/LD is low; parallel input setup time is 10 ns minimum."
      },
      {
        "number": "15",
        "name": "CLK INH",
        "type": "input",
        "description": "Clock inhibit input: holding it high inhibits clocking, and it should be changed to the high level only while CLK is high."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, 4.75 V minimum, 5 V nominal, 5.25 V maximum per the recommended operating conditions."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The extracted text shows 'QH' twice (pins 7 and 9); the overbar on the complementary output was lost; Pin numbers were assigned from the TOP VIEW block, where the number-to-name order was scrambled in e; The datasheet's DIP drawing on page 9 is an image with no extractable pin text, so the pinout rests "
        ],
        "pages_sent": 10,
        "cost_usd": 0.0449,
        "at": "2026-10-25T19:09:35"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/eabd153fd377df654dd7c9acc6d0ff6e.pdf",
        "pages": 10,
        "sha256": "0d0e0e24042cca96",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "xd74ls165.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          19.177,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "17a30b1f0ab3fd5384a1231e3c63c394888d5b952c542a8c189e023ed3467464",
        "checked": "2026-10-25",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "xd74ls165-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          19.177,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "1d43ec809b18efe6c4e98b15c6bea711ae268ab838b9765a9aea7ab7eb105418",
        "checked": "2026-10-25",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}