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Generated by kicad-footprint-generator · KiCad file format 20260206

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XCF02SVOG20C

XILINX · CPLD/FPGA · TSSOP-20

XCF02SVOG20C from XILINX, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D0	tri_state	DATA output pin providing data for configuring an FPGA in serial mode, set to high-impedance during ISPEN (when not clamped).
2	DNC	unconnected	Do not connect; this pin must be left unconnected.
3	CLK	input	Configuration clock input; each rising edge increments the internal address counter if CLK is selected, CE is Low and OE/RESET is High.
4	TDI	input	JTAG serial data input to all instruction and data registers, with an internal 50 kΩ pull-up to VCCJ.
5	TMS	input	JTAG mode select input sampled on rising edge of TCK to determine TAP state transitions, with an internal 50 kΩ pull-up to VCCJ.
6	TCK	input	JTAG test clock input that sequences the TAP controller and all JTAG test and programming electronics.
7	CF	output	Configuration pulse open-drain output, pulsed Low by the JTAG CONFIG command to initiate FPGA configuration without powering down the FPGA.
8	OE/RESET	bidirectional	Open-drain output enable/reset I/O; when Low it holds the address counter reset and DATA in high-impedance, and it is held Low during internal power-on reset.
9	DNC	unconnected	Do not connect; this pin must be left unconnected.
10	CE	input	Chip enable input; when High the device enters low-power standby, the address counter is reset and DATA pins are high-impedance.
11	GND	power_in	Ground.
12	DNC	unconnected	Do not connect; this pin must be left unconnected.
13	CEO	output	Chip enable output connected to the CE input of the next PROM in the chain, Low when CE is Low, OE/RESET is High and the address counter is beyond its terminal count.
14	DNC	unconnected	Do not connect; this pin must be left unconnected.
15	DNC	unconnected	Do not connect; this pin must be left unconnected.
16	DNC	unconnected	Do not connect; this pin must be left unconnected.
17	TDO	output	JTAG serial data output for all instruction and data registers, with an internal 50 kΩ pull-up to VCCJ.
18	VCCINT	power_in	+3.3V supply voltage for internal logic.
19	VCCO	power_in	+3.3V, 2.5V, or 1.8V I/O supply connected to the output voltage drivers and input buffers.
20	VCCJ	power_in	+3.3V or 2.5V JTAG I/O supply connected to the TDO output driver and TCK, TMS, and TDI input buffers.

Key specifications

Parameter	Value
Manufacturer	XILINX
Package	TSSOP-20
Category	Embedded Processors & Controllers
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Internal supply voltage	VCCINT	-0.5		4	V	relative to GND	13
I/O supply voltage	VCCO	-0.5		4	V	relative to GND	13
JTAG I/O supply voltage	VCCJ	-0.5		4	V	relative to GND	13
Input voltage	VIN	-0.5		3.6	V	VCCO < 2.5V	13
Input voltage	VIN	-0.5		5.5	V	VCCO ≥ 2.5V	13
Voltage applied to High-Z output	VTS	-0.5		3.6	V	VCCO < 2.5V	13
Voltage applied to High-Z output	VTS	-0.5		5.5	V	VCCO ≥ 2.5V	13
Storage temperature (ambient)	TSTG	-65		150	°C		13
Junction temperature	TJ			125	°C		13
VCCINT rise time	TVCC	0.2		50	ms	0V to nominal voltage	13
POR threshold for VCCINT	VCCPOR	1			V		13
OE/RESET release delay following POR	TOER	0.5		3	ms		13
Power-down threshold for VCCINT	VCCPD			1	V		13
Time to trigger reset when VCCINT drops below VCCPD	TRST	10			ms		13
Internal voltage supply	VCCINT	3	3.3	3.6	V		14
Supply voltage for output drivers	VCCO	3	3.3	3.6	V	3.3V Operation	14
Supply voltage for output drivers	VCCO	2.3	2.5	2.7	V	2.5V Operation	14
Supply voltage for output drivers	VCCO	1.7	1.8	1.9	V	1.8V Operation	14
Supply voltage for JTAG output drivers	VCCJ	3	3.3	3.6	V	3.3V Operation	14
Supply voltage for JTAG output drivers	VCCJ	2.3	2.5	2.7	V	2.5V Operation	14
Low-level input voltage	VIL	0		0.8	V	3.3V Operation	14
Low-level input voltage	VIL	0		0.7	V	2.5V Operation	14
High-level input voltage	VIH	2		5.5	V	3.3V Operation	14
High-level input voltage	VIH	1.7		5.5	V	2.5V Operation	14
Input signal transition time	TIN			500	ns	measured between 10% VCCO and 90% VCCO	14
Operating ambient temperature	TA	-40		85	°C		14
Data retention	TDR	20			Years		14
Program/erase cycles (Endurance)	NPE	20000			Cycles		14
Electrostatic discharge	VESD	2000			Volts		14
High-level output voltage for 3.3V outputs	VOH	2.4			V	IOH = -4 mA	15
Low-level output voltage for 3.3V outputs	VOL			0.4	V	IOL = 4 mA	15
Low-level output voltage for 2.5V outputs	VOL			0.4	V	IOL = 500 µA	15
Low-level output voltage for 1.8V outputs	VOL			0.4	V	IOL = 50 µA	15
Internal voltage supply current, active mode	ICCINT			10	mA	33 MHz	15
Output driver supply current, active serial mode	ICCO			10	mA	33 MHz	15
JTAG supply current, active mode	ICCJ			5	mA	Note (2)	15
Internal voltage supply current, standby mode	ICCINTS			5	mA	Note (3)	15
Output driver supply current, standby mode	ICCOS			1	mA	Note (3)	15
JTAG supply current, standby mode	ICCJS			1	mA	Note (3)	15
JTAG pins TMS, TDI, and TDO pull-up current	IILJ			100	µA	VCCJ = max, VIN = GND	15
Input leakage current	IIL	-10		10	µA	VCCINT = max, VCCO = max, VIN = GND or VCCO	15
Input and output High-Z leakage current	IIH	-10		10	µA	VCCINT = max, VCCO = max, VIN = GND or VCCO	15
Input capacitance	CIN			8	pF	VIN = GND, f = 1.0 MHz	15
Output capacitance	COUT			14	pF	VIN = GND, f = 1.0 MHz	15
TCK minimum clock period	TCKMIN	67			ns	VCCJ = 2.5V or 3.3V	7
TMS setup time	TMSS	8			ns	VCCJ = 2.5V or 3.3V	7
TMS hold time	TMSH	25			ns	VCCJ = 2.5V or 3.3V	7
TDI setup time	TDIS	8			ns	VCCJ = 2.5V or 3.3V	7
TDI hold time	TDIH	25			ns	VCCJ = 2.5V or 3.3V	7
TDO valid delay	TDOV			22	ns	VCCJ = 2.5V or 3.3V	7
CF hold time to guarantee design revision selection is sampled	THCF	300			ns	VCCO = 3.3V or 2.5V	16
OE/RESET to data delay	TOE			10	ns	VCCO = 3.3V or 2.5V	16
CE to data delay	TCE			15	ns	VCCO = 3.3V or 2.5V	16
CLK to data delay	TCAC			15	ns	VCCO = 3.3V or 2.5V	16
Data hold from CE, OE/RESET, CLK, or CF	TOH	0			ns	VCCO = 3.3V or 2.5V	16
CE or OE/RESET to data float delay	TDF			25	ns	VCCO = 3.3V or 2.5V	16
Clock period (serial mode)	TCYC	30			ns	VCCO = 3.3V or 2.5V	17
CLK Low time	TLC	10			ns	VCCO = 3.3V or 2.5V	17
CLK High time	THC	10			ns	VCCO = 3.3V or 2.5V	17

CAD (KiCad official)

Symbol: XCF02SVOG20C
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: xcf02svog20c-etched.step / xcf02svog20c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xcf02svog20c.step / xcf02svog20c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XILINX datasheet (35 pp, sha256 a9dea23235e03c9b, retrieved 2026-10-23, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF